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motorola semiconductor technical data dsp56167 order this doc u ment b y: dsp56167/d, rev. 1 ?1996, 1997 motorola, inc. this document contains information on a new product. specifications and information herein are subject to change without notice. preliminary advance information 16-bit digital signal processor the general-purpose, programmable dsp56167 is an enhanced version of the dsp56166 with added features. designed primarily for speech coding and digital communications, the dsp56167 has a built-in sd codec and phase lock loop (pll). this mpu-style dsp also contains memories and digital peripherals that provide a cost effective, high performance solution to many dsp applications. on-chip emulation (once ? ) circuitry provides convenient and inexpensive debug facilities normally available only through expensive external hardware. this ram-based dsp contains a 2 k 16 program ram and a 4 k 16 data ram. the central processing unit (cpu) consists of three execution units operating in parallel allowing up to six operations to occur in an instruction cycle. this parallelism greatly increases the effective processing speed of the dsp56167. the mpu-style programming model and instruction set allow straightforward generation of efficient, compact code. the dsp56167 is a member of motorolas dsp56100 family of 16-bit digital signal processors (dsps). figure 1 dsp56167 block diagram xdb pdb gdb 4 7+10 address port a program control unit moda/irqa modb/irqb on-chip peripherals: host, ssi0, ssi1, timer gpio, codec internal data bus switch and bit manipulation unit external address bus switch bus control external data bus switch program ram 2 k 16 data ram 4 k 16 program address generator program decode controller program interrupt controller data alu 16 16 + 40 ? 40-bit mac two 40-bit accumulators clock and pll extal port b or host 15 codec, port c and/or ssi0, ssi1, timer reset 16 bits data 10 once? sxfc clko xab1 xab2 pab address generation unit 16 16 modc/irqc peripheral address generation unit external chip enables 2 bootstrap rom 64 16 aa0771
ii dsp56167/d, rev. 1 motorola table of contents preliminary table of contents section 1 signal/pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 section 2 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 section 3 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 section 4 design considerations (includes notes for dsp56166 to dsp56167 design conversion) . . . . . . . . 4-1 section 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 for technical assistance: telephone: 1 (800) 521-6274 email: dsphelp@dsp.sps.mot.com internet: http://www.motorola-dsp.com data sheet conventions t his data sheet uses the following conventions: overbar used to indicate a signal that is active when pulled low; for example, the reset pin is active when low asserted means that a high true (active high) signal is high or that a low true (active low) signal is low deasserted means that a high true (active high) signal is low or that a low true (active low) signal is high examples: signal/symbol logic state signal state voltage pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol note: values for v il , v ol , v ih , and v oh are defined by individual product specifications.
features motorola dsp56167/d, rev. 1 iii preliminary features ? digital signal processing core C up to 30 million instructions per second (mips) at 60 mhz with 33.3 ns instruction cycle C single-cycle 16 16-bit parallel multiply-accumulate C2 40-bit accumulators with extension byte C fractional and integer arithmetic with support for multiprecision arithmetic C highly parallel instruction set with unique dsp addressing modes C nested hardware do loops including infinite loops and do zero loop C two instruction lms adaptive filter loop C fast auto-return interrupts C three external interrupt request pins C three 16-bit internal data and three 16-bit internal address buses C individual programmable wait states on the external bus for program, data, and peripheral memory spaces C programmable absolute short addressing mode C off-chip memory-mapped peripheral space with programmable access time and separate peripheral enable pin C peripheral address generation unit (pagu) C on-chip memory-mapped peripheral registers C on-chip emulation (once ? ) port for unobtrusive, processor speed- independent debugging with dr line static latch with reset ? memory C modified harvard architecture permits simultaneous accesses to program and data memories C 2 k 16-bit on-chip program ram C 4 k 16-bit on-chip data ram C 64 16-bit bootstrap rom C external memory expansion with 16-bit address and data buses with static latches with reset and software-controlled bg pull-down C bootstrap loading from external byte-wide program rom, host interface, or 16-bit synchronous serial interface (ssi0)
iv dsp56167/d, rev. 1 motorola features preliminary ? peripherals C up to twenty-five general purpose input/output (gpio) pins, depending on which peripherals are enabled C byte-wide host interface with direct memory access (dma) support (or up to fifteen port b gpio lines) C on-chip sd voice band codec, analog-to-digital (a/d) and digital-to- analog (d/a) ? internal voltage reference (1/2 of positive power supply) and split- voltage operation (with respect to the core) ? no off-chip components required C 16-bit ssi support: two 4-pin ports (or up to eight port c gpio lines) C one 16-bit timer/event counter (or two port c gpio lines) C double-buffered peripherals C independent external chip enables br and peren during bus master mode C software-programmable, phase lock loop-based (pll) frequency synthesizer for the dsp core clock with a wide input frequency range (12.2 khz to 60 mhz) that initializes to a preset low frequency operation during hardware reset ? energy efficient design C power-saving wait and stop modes C fully static, hcmos design allows operation from 60 mhz down to dc operating frequencies C 112-pin plastic thin quad flat pack (tqfp) surface-mount package
product documentation motorola dsp56167/d, rev. 1 v preliminary product documentation the three documents listed in the following table are required for a complete description of the dsp56167 and are necessary to design properly with the part. documentation is available from one of the following locations (see back cover for detailed information): ? a local motorola distributor ? a motorola semiconductor sales office ? a motorola literature distribution center ? the world wide web (www) (the source for the latest information) table 1 dsp56167 documentation name description order number dsp56100 family manual detailed description of the dsp56100 family processor core and instruction set dsp56100fm/ad dsp56167 users manual detailed functional description of the dsp56167 memory configuration, operation, and register programming see note below dsp56167 technical data dsp56167 features list and physical, electrical, timing, and package specifications dsp56167/d note: the dsp56167 users manual is currently being developed and will not be available for general release until the end of the second quarter of 1997. the dsp56167 is a feature expanded, enhanced version of the dsp56166 and is entirely software compatible. until the dsp56167 users manual is available, the user can refer to the dsp56166 users manual , order number dsp56166um/ad for information common to both chips and section 4 of this document for a description of the added features and enhanced capability of the dsp56167.
vi dsp56167/d, rev. 1 motorola product documentation preliminary
motorola dsp56167/d, rev. 1 1-1 preliminary section 1 signal/pin descriptions introduction dsp56167 signals are organized into thirteen functional groups as summarized in table 1-1 . figure 1-1 is a diagram of dsp56167 signals by functional group. table 1-1 signal functional group allocations functional group number of signals detailed description power (v ddx )11 table 1-2 ground (v ssx )16 table 1-3 pll and clock 3 table 1-4 address bus port a 1 16 table 1-5 data bus 16 table 1-6 bus control 10 table 1-7 interrupt and mode control 4 table 1-8 host interface (hi) port port b 2 15 table 1-9 codec 7 table 1-10 16-bit synchronous serial interface (ssi0) port port c 3 4 table 1-11 16-bit synchronous serial interface (ssi1) port 4 table 1-12 timer 2 table 1-13 on-chip emulation (once) port 4 table 1-14 note: 1. port a signals define the external memory interface port. 2. port b signals are gpio signals multiplexed on the external pins also used with the hi signals. 3. port c signals are gpio signals multiplexed on the external pins also used by the ssi ports and the timer.
1-2 dsp56167/d, rev. 1 motorola signal/pin descriptions introduction preliminary figure 1-1 signals identified by functional group dsp56167 16 16 external address bus external data bus external bus control codec 16-bit synchronous serial interface (ssi1) port 2 timer 2 pll and clock once port power inputs: pll and clock address and data bus bus control internal logic port b codec port c a0-a15 d0-d15 bs ps/ds peren wr rd r/w ta br bg bb dsi/os0 dsck /os1 dso dr extal clko sxfc v dds v dda/d v ddc v ddq v ddpb v dda v ddpc 4 16-bit synchronous serial interface (ssi0) port 2 2 grounds: pll and clock address and data bus bus control internal logic port b codec port c gnd s v ssa/d v ssc v ssq v sspb v ssa v sspc 8 2 2 interrupt/ mode control moda/irqa modb/irqb modc/irqc reset mic aux spkp spkm v rad v rda v div host interface port 1 pb0/h0Cpb7/h7 pb8/ha0Cpb10/ha2 pb11/hr/w pb12/hen pb13/hreq pb14/hack pc0/std0 pc1/srd0 pc2/sck0 pc4/sfs0 pc5/std1 pc6/srd1 pc7/sck1 pc9/sfs1 pc10/tin pc11/tout 8 3 note: 1. the hi port signals are multiplexed with the port b gpio signals (pb0Cpb14). 2. the 16-bit ssi and timer signals are multiplexed with the port c gpio signals (pc0Cpc2, pc4Cpc7, and pc9Cpc11). aa0772
signal/pin descriptions power motorola dsp56167/d, rev. 1 1-3 preliminary power table 1-2 power power names description v dds synthesizer power this line is dedicated to the pll circuits and must remain noise-free to ensure stable pll frequency and performance. ensure that the input voltage to this line is well-regulated and uses an extremely low impedance path to tie to the v dd power rail. use a 0.1 m f capacitor and a 0.01 m f capacitor located as close as possible to the chip package to connect between the v dds line and the gnd s line. v dda/d address and data bus power these lines supply power to the address and data busses. v ddc bus control power this line supplies power to the bus control logic. v ddq quiet power these lines supply a quiet power source to the internal logic circuits. ensure that the input voltage to this line is well-regulated and uses an extremely low impedance path to tie to the v dd power rail. use a 0.1 m f bypass capacitor located as close as possible to the chip package to connect between the v ddq lines and the v ssq lines. v ddpb port b power these lines supply power to the port b hi logic. v dda codec power this line supplies power to the codec logic. v ddpc port c power this line supplies power to the ssi and timer logic.
1-4 dsp56167/d, rev. 1 motorola signal/pin descriptions ground preliminary ground table 1-3 ground ground names description gnd s synthesizer ground this line supplies a dedicated quiet ground connection for the pll and clock circuits and must remain relatively noise-free to ensure stable pll frequency and performance. ensure that this line connects through an extremely low impedance path to ground. use a 0.1 m f capacitor and a 0.01 m f capacitor located as close as possible to the chip package to connect between the v dds line and the gnd s line. v ssa/d address and data bus ground these lines connect system ground to the address bus. v ssc bus control ground this line connects ground to the bus control logic. v ssq (4) quiet ground these lines supply a quiet ground connection for the internal logic circuits. ensure that this line connects through an extremely low impedance path to ground. use a 0.1 m f bypass capacitor located as close as possible to the chip package to connect between the v ddq line and the v ssq line. v sspb port b host interface ground these lines supply ground connections for the port b hi logic. v ssa codec power this line supplies a ground connection to the codec logic. v sspc port c power this line supplies a ground connection to the ssi and timer logic.
signal/pin descriptions pll and clock motorola dsp56167/d, rev. 1 1-5 preliminary pll and clock address bus table 1-4 pll and clock signals signal name signal type state during reset signal description extal input input external clock/crystal input this input should be connected to an external crystal or to an external oscillator. a sine wave with a minimum swing of 1 v p can be applied to this pin. after being squared, the input clock can provide the dsp core clock directly. internally, the clock is divided to produce a four-phase instruction clock (t0, t1, t2, and t3) with the instruction clock period being equal to two input clock periods. this input clock can also be selected as the input clock for the on-chip codec and pll. clko output chip- driven pll output clock this buffered clock signal output can be one of three signals, selected by programming the two bits, cs1 and cs2 in the pll control register (plcr): ? a squared version of the extal input ? a squared version of the extal input divided by 2 ? a delayed version of the dsp core master clock clko can be disabled by setting the clockout disable (cd) bit 7 of the operating mode register (omr). note: for information about programming the plcr or omr, see the dsp56100 family manual . sxfc input input external filter capacitor connect an external capacitor to the filter circuit of the pll between this input and v dds . see section 2 of this document for additional information about capacitor size selection. table 1-5 address bus signals signal names signal type state during reset signal description a0Ca15 output tri-stated address bus these signals change in t0 and specify the address for external program and data memory accesses. if there is no external bus activity, a0Ca15 remain at their previous values to reduce power consumption.
1-6 dsp56167/d, rev. 1 motorola signal/pin descriptions data bus preliminary data bus bus control table 1-6 data bus signals signal names signal type state during reset signal description d0Cd15 input/ output tri-stated data bus these signals provide the bidirectional data bus for external program and data memory accesses. read data is sampled in by the trailing edge of t2, while write data output is enabled by the leading edge of t2 and tri-stated at the leading edge of t0. d0Cd15 are tri-stated when there is no bus activity. table 1-7 bus control signals signal name signal type state during reset signal description bs output pulled high bus select bs is asserted when the dsp accesses the external bus, and it acts as an early indication of imminent external bus access by the dsp56167. it may also be used with the bus wait input wt to generate wait states. bs is pulled high when the bg or reset signal is asserted. ps/ds output tri-stated program/data memory select this signal is asserted high for external program memory access and low for external data memory access. the timing is the same as for the address bus signals a0C a15. if the external bus is not used during an instruction cycle, ps/ ds goes high at the next t0. peren output tri-stated peripheral enable this output is asserted only when the external peripheral data memory space (x:$ff00Cx:$ff7f) is referenced. the timing is the same as for the address bus signals a0Ca15. the signal is asserted and deasserted in t0. peren is driven high for any program space access and for any data memory access outside of the peripheral data memory address range. wr output tri-stated write enable wr is asserted low during external memory write cycles. when wr is asserted in t1, the data bus signals (d0Cd15) become outputs. the dsp puts data on the bus on the leading edge of t2. when wr is deasserted in t3, the data should be latched in the external device. the signal qualifies a0Ca15 and ps/ds . wr is tri-stated when the dsp is not the bus master. wr can be connected directly to the we pin of a static ram chip.
signal/pin descriptions bus control motorola dsp56167/d, rev. 1 1-7 preliminary rd output tri-stated read enable rd is asserted low during external memory read cycles. when rd is asserted in late t0/early t1, the data bus signals (d0Cd15) become inputs and an external device is enabled on the data bus. when rd is deasserted in t3, the data is latched in the dsp. the signal qualifies a0Ca15 and ps/ds . rd is tri-stated when the dsp is not the bus master. rd can be connected directly to the oe pin of a rom or static ram. r/w output tri-stated read/write the timing for this signal is the same as the bus address lines, providing an early write signal. r/w changes in t0 and is high for a read access and low for a write access. if the external bus is not used during an instruction cycle, r/w goes high at the next t0. ta input input transfer acknowledge when there is external bus cycle activity, ta can be used to insert wait states (ws) in the external bus cycle. ta is sampled on the leading edge of the clock input. if ta is sampled high, the bus cycle will end 2t after ta is sampled low, assuming the bus control register (bcr) is not programmed to insert its own ws. the number of ws is determined by ta and the bcr and is equal to the larger of the two determining sources. ta continues to be sampled as the bcr ws number decrements. if ta is sampled low, but there are remaining ws required by the bcr, the bus cycle continues until the bcr requirement is satisfied. if the bcr requirement is satisfied, but ta has not been sampled low, the ws continue until 2t after ta is sampled low. to be sampled high at the start of the bus cycle, ta must be driven high in t3 on the previous instruction cycle. if ta is sampled low at t0 of a bus cycle and no ws are specified by the bcr, no ws are inserted in the external bus cycle. if there is no external bus activity, the dsp ignores ta . table 1-7 bus control signals (continued) signal name signal type state during reset signal description
1-8 dsp56167/d, rev. 1 motorola signal/pin descriptions bus control preliminary br input or output input bus request after reset, this signal is an input (slave mode). when the br input is asserted, an external device, such as another processor or dma controller, becomes the master of the external address and data buses. the dsp asserts the bg output signal after a few t states (i.e., t0, t1, etc.) to acknowledge the br input. the dsp releases control of the external bus at the earliest possible time consistent with proper synchronization. at release, the dsp tri- states peren , ps/ds , rd , wr , and r/w , and deasserts the bb signal to indicate the bus is released. while the bus is released, the dsp may continue internal operations using internal memory spaces. if external access is required, the dsp bus controller inserts ws until the bus is available. bus control returns to the dsp when the br and bb inputs are both deasserted. note: interrupts are not serviced while a dsp instruction is waiting for the bus. note: br cannot interrupt the execution of a read-modify-write instruction. if the master bit in the operating mode register (omr) is set, this signal is an output (master mode). in this mode the dsp is not the default bus master and must assert br to gain control of the external bus. after asserting br , the dsp bus controller inserts ws until the bg input is asserted. the dsp begins processing external accesses on the rising edge of the clock after bb is sampled high. br remains asserted until the dsp no longer needs the bus. in master mode, the request hold (rh) bit in the bcr allows br to be asserted under software control. note: during external accesses caused by an instruction executed out of external program memory, br remains asserted for consecutive external x data memory accesses and continues toggling for consecutive external program memory accesses until rh in the bcr is set. note: in master mode, br can also be used for non-arbitration uses. if bg is always asserted, br is asserted in t0 of every external bus access. in this case, br can act as a chip select signal to enable and disable an external memory device between external and internal accesses. in this case, the br timing is similar to a0Ca15, r/w , and ps/ds and is asserted and deasserted in t0. table 1-7 bus control signals (continued) signal name signal type state during reset signal description
signal/pin descriptions bus control motorola dsp56167/d, rev. 1 1-9 preliminary bg output or input driven high bus grant after reset, this signal is an output (slave mode) that is asserted to acknowledge an external device request for bus control (i.e., assertion of a br input). the dsp asserts the bg output signal after a few t states to acknowledge receipt of the br input. the dsp releases control of the external bus at the earliest possible time consistent with proper synchronization. at release, the dsp tri- states peren , ps/ds , rd , wr , and r/w and deasserts the bb output. when the br and bb inputs are deasserted, the dsp regains control of the bus and the bg output is deasserted. note: bg may be asserted in the middle of an instruction that requires more than one external bus cycle for execution, but never during a read-modify-write instruction. if the master bit in the omr is set, this signal is an input (master mode). in this mode the external bus master asserts b g to acknowledge the br signal generated by the dsp to request control of the bus. the dsp begins processing external accesses on the rising edge of the clock after the bb input generated by the other bus master is sampled high. when the bg input is deasserted, the dsp releases the bus as soon as the current transfer is complete. bb input or output input bus busy after reset, this signal is an input. an external master asserts this input signal to indicate that it has control of the bus and is performing a bus access. when the dsp acquires control of the external bus and performs and external access, it asserts bb as an output signal to the other bus master devices. the dsp deasserts bb and it again becomes an input when the dsp releases bus control. table 1-7 bus control signals (continued) signal name signal type state during reset signal description
1-10 dsp56167/d, rev. 1 motorola signal/pin descriptions interrupt and mode control preliminary interrupt and mode control table 1-8 interrupt and mode control signals signal name signal type state during reset signal description moda/irqa input input mode select a/external interrupt request a this input has two functions: 1. to select the initial chip operating mode, and 2. after synchronization, to allow an external device to request a dsp interrupt. moda is read and internally latched in the dsp when the processor exits the reset state. moda, modb, and modc select the initial chip operating mode. several clock cycles (depending on pll stabilization time) after leaving the reset state, the moda signal changes to external interrupt request irqa . the chip operating mode can be changed by software after reset. the irqa input is a synchronized external interrupt request that indicates that an external device is requesting service. it may be programmed to be level-sensitive or negative-edge-sensitive. if level-sensitive triggering is selected, an external pull up resistor is required for wired-or operation. if the processor is in the stop state and irqa is asserted, the processor will exit the stop state. modb/irqb input input mode select b/external interrupt request b this input has two functions: 1. to select the initial chip operating mode, and 2. after internal synchronization, to allow an external device to request a dsp interrupt. modb is read and internally latched in the dsp when the processor exits the reset state. moda, modb, and modc select the initial chip operating mode. several clock cycles (depending on pll stabilization time) after leaving the reset state, the modb signal changes to external interrupt request irqb . after reset, the chip operating mode can be changed by software. the irqb input is an external interrupt request that indicates that an external device is requesting service. it may be programmed to be level-sensitive or negative-edge- triggered. if level sensitive triggering is selected, an external pull up resistor is required for wired-or operation.
signal/pin descriptions interrupt and mode control motorola dsp56167/d, rev. 1 1-11 preliminary modc/irqc input input mode select c/external interrupt request c this input has two functions: 1. to select the initial chip operating mode, and 2. after synchronization, to allow an external device to request a dsp interrupt. modc is read and internally latched in the dsp when the processor exits the reset state. moda, modb, and modc select the initial chip operating mode. several clock cycles (depending on pll stabilization time) after leaving the reset state, the modc signal changes to external interrupt request irq c. after reset, the chip operating mode can be changed by software. the irq c input is an external interrupt request that indicates that an external device is requesting service. it may be programmed to be level-sensitive or negative-edge- triggered. if level sensitive triggering is selected, an external pull up resistor is required for wired-or operation. reset input input reset this input is a direct hardware reset on the processor. when reset is asserted low, the dsp is initialized and placed in the reset state. a schmitt trigger input is used for noise immunity. when the reset signal is deasserted, the initial chip operating mode is latched from the moda, modb, and modc signals. the internal reset signal is deasserted synchronous with the internal clocks. table 1-8 interrupt and mode control signals (continued) signal name signal type state during reset signal description
1-12 dsp56167/d, rev. 1 motorola signal/pin descriptions host interface (hi) port preliminary host interface (hi) port table 1-9 hi signals signal name signal type state during reset signal description h0Ch7 pb0Cpb7 input/ output tri-stated host data bus (h0Ch7) this data bus transfers data between the host processor and the dsp56167. the bus signals are inputs except when hr/w is high and hen is asserted (host read). port b gpio 0C7 (pb0Cpb7) these signals are gpio signals (pb0Cpb7) when the host interface is not selected. after reset, the default state for these signals is gpio input. ha0Cha2 pb8Cpb10 input input/ output tri-stated host address 0 C host address 2 (ha0Cha2) these inputs provide the address selection for each host interface register and are stable when hen is asserted. port b gpio 8C10 (pb8Cpb10) these signals are gpio signals (pb8Cpb10) when the host interface is not selected. after reset, the default state for these signals is gpio input. hr/w pb11 input input/ output tri-stated host read/write this input selects the direction of data transfer for each host processor access. if hr/w is high and hen is asserted, h0Ch7 are outputs and dsp data is transferred to the host processor. if hr/w is low and hen is asserted, h0C h7 are inputs and host data is transferred to the dsp. hr/w is stable when hen is asserted. port b gpio 11 (pb11) this signal is a gpio signal (pb11) when the host interface is not being used. after reset, the default state for this signal is gpio input. hen pb12 input input/ output tri-stated host enable this input enables a data transfer on the host data bus. when hen is asserted and hr/w is high, h0Ch7 are outputs and dsp data is transferred to the host processor. if hr/w is low and hen is asserted, h0Ch7 are inputs and host data is transferred to the dsp. this input may be used as a chip select input from the external host. port b gpio 12 (pb12) this signal is a gpio signal (pb12) when the host interface is not being used. after reset, the default state for this signal is gpio input.
signal/pin descriptions host interface (hi) port motorola dsp56167/d, rev. 1 1-13 preliminary hreq pb13 open drain output input/ output tri-stated host request this signal is used by the host interface to request service from the host processor, dma controller, or a simple external controller. hreq is asserted when an enabled request occurs in the hi. the signal is deasserted when the request is cleared or masked, the dma controller asserts hack , or the dsp is reset. port b gpio 13 (pb13) this signal is a general purpose (not open-drain) i/o signal (pb13) when the host interface is not selected. after reset, the default state for this signal is gpio input. hack pb14 input input/ output tri-stated host acknowledge this input has two functions: 1. host acknowledge handshake signal hack may be used as a data strobe for hi dma data transfers 2. mc68000 host interrupt acknowledge this function enables the hi interrupt vector register (ivr) onto the hi data bus if the hreq output is asserted. in this case, all other hi control pins are ignored and the hi state is not affected. port b gpio 14 (pb14) this signal is a gpio signal (pb14) when the host interface is not selected. after reset, the default state for this signal is gpio input. table 1-9 hi signals (continued) signal name signal type state during reset signal description
1-14 dsp56167/d, rev. 1 motorola signal/pin descriptions codec preliminary codec table 1-10 codec signals signal name signal type state during reset signal description aux input input auxiliary input this signal is selected as the analog input to the a/d converter when the ins bit in codec control register 1 (ccr1) is set. leave this pin floating when the codec is not used. mic input input microphone input this signal is selected as the analog input to the a/d converter when the ins bit in ccr1 is cleared. leave this pin floating when the codec is not used. spkp output speaker output 1 this signal is the negative analog output from the on-chip d/a converter. leave this pin floating when the codec is not used. in the codec power down mode, this signal connects internally to vdiv through a high impedance path. spkm output speaker output 2 this signal is the positive analog output from the on-chip d/a converter. leave this pin floating when the codec is not used. in the codec power down mode, this signal connects internally to vdiv through a high impedance path. vrad output voltage reference output for a/d this is the output from the op-amp buffer in the a/d sections reference voltage generator. it has a value of 1/2 v dda . this voltage is used as the analog ground internal to the a/d block. always connect this pin to ground through two capacitors even when the codec is not used. in codec power down mode, the vrad signal is tri-stated. vrda output voltage reference output for d/a this is the output from the op-amp buffer in the d/a sections reference voltage generator. it has a value of 1/2 v dda . this voltage is used as the analog ground internal to the d/a block. always connect this pin to ground through two capacitors even when the codec is not used. in codec power down mode, the vrda signal is tri-stated. vdiv output voltage division output this is the input to the op-amp buffer in the reference voltage generator. it is connected to a resistor divider network located within the codec block that provides a voltage equal to 1/2 v dda . leave this pin floating when the codec is not used. this output is not affected by codec power down mode. note: the spkp and spkm outputs consist of a fully differential driver stage, with each output having an operating range of 1.0 v p from vrda. the output op-amp can provide up to 0.35 ma of current which can drive a resistive load of 3 k w in series with 15 nf capacitance between the differential outputs.
signal/pin descriptions 16-bit synchronous serial interface 0 port motorola dsp56167/d, rev. 1 1-15 preliminary 16-bit synchronous serial interface 0 port table 1-11 16-bit synchronous serial interface 0 (ssi0) signals signal name signal type state during reset signal description std0 pc0 output tri- stated serial transmit data 0 (std0) this output transmits serial data from the ssi0 transmit shift register (tsr0). port c gpio 0 (pc0) this signal is a gpio signal (pc0) when the ssi0 std0 function is not being used. after reset, the default state is gpio input. srd0 pc1 input tri- stated serial receive data 0 (srd0) the input receives serial data into the ssi0 receive shift register (rsr0). port c gpio 1 (pc1) this signal is a gpio signal (pc1) when the ssi0 srd0 function is not being used. after reset, the default state is gpio input. sck0 pc2 input/ output tri- stated serial clock 0 (sck0) this bidirectional signal provides the serial bit rate clock for the ssi0 interface. the clock signal can be continuous or gated and is used by both the transmitter and receiver. port c gpio 5 (pc5) this signal is a gpio signal (pc2) when the ssi0 sck0 function is not being used. after reset, the default state is gpio input. sfs0 pc4 input/ output tri- stated serial frame sync 0 this bidirectional signal is used by the ssi0 serial interface for frame sync i/o or flag i/o. the sfs0 is used by both the transmitter and receiver to synchronize data transfer and can be an input or an output. port c gpio 4 (pc4) this signal is a gpio signal (pc4) when the ssi0 sfs0 function is not being used. after reset, the default state is gpio input.
1-16 dsp56167/d, rev. 1 motorola signal/pin descriptions 16-bit synchronous serial interface 1 port preliminary 16-bit synchronous serial interface 1 port table 1-12 16-bit synchronous serial interface 1 (ssi1) signals signal name signal type state during reset signal description std1 pc5 output tri- stated serial transmit data 1 (std1) this output transmits serial data from the ssi1 transmit shift register (tsr1). port c gpio 5 (pc5) this signal is a gpio signal (pc5) when the ssi1 std1 function is not being used. after reset, the default state is gpio input. srd1 pc6 input tri- stated serial receive data 0 (srd0) the input receives serial data into the ssi1 receive shift register (rsr1). port c gpio 6 (pc6) this signal is a gpio signal (pc6) when the ssi1 srd1 function is not being used. after reset, the default state is gpio input. sck1 pc7 input/ output tri- stated serial clock 1 (sck1) this bidirectional signal provides the serial bit rate clock for the ssi1 interface. the clock signal can be continuous or gated and is used by both the transmitter and receiver. port c gpio 7 (pc7) this signal is a gpio signal (pc7) when the ssi1 sck1 function is not being used. after reset, the default state is gpio input. sfs0 pc9 input/ output tri- stated serial frame sync 1 this bidirectional signal is used by the ssi1 serial interface for frame sync i/o or flag i/o. the sfs1 is used by both the transmitter and receiver to synchronize data transfer and can be an input or an output. port c gpio 9 (pc9) this signal is a gpio signal (pc9) when the ssi1 sfs1 function is not being used. after reset, the default state is gpio input.
signal/pin descriptions timer motorola dsp56167/d, rev. 1 1-17 preliminary timer table 1-13 timer signals signal name signal type state during reset signal description tin pc10 input tri- stated timer input this input signal receives external pulses to be counted by the on-chip 16-bit timer when external clocking is selected. the pulses are internally synchronized to the dsp core internal clock. port c gpio 10 (pc10) this signal is a gpio signal (pc10) when the timer function is not being used. tio1 pc11 input/ output tri- stated timer output this output generates pulses, toggles on a timer overflow event, or toggles on a compare event. port c gpio 11 (pc11) this signal is a gpio signal (pc11) when the timer function is not being used.
1-18 dsp56167/d, rev. 1 motorola signal/pin descriptions on-chip emulation port preliminary on-chip emulation port table 1-14 on-chip emulation (once) port signals signal name signal type state during reset signal description dsi/os0 input/ output low output debug serial input/chip status 0 serial data or commands are provided to the once controller through the dsi/os0 signal when it is an input. the data received on the dsi signal will be recognized only when the dsp has entered the debug mode of operation. data is latched on the falling edge of the dsck serial clock. data is always shifted into the once serial port most significant bit (msb) first. when the dsi/os0 signal is an output, it works in conjunction with the os1 signal to provide chip status information. the dsi/os0 signal is an output when the processor is not in debug mode. when switching from output to input, the signal is tri-stated. dsck/os1 input/ output low output debug serial clock/chip status 1 the dsck/os1 signal supplies the serial clock to the once port when it is an input. the serial clock provides pulses required to shift data into and out of the once serial port. (data is clocked into the once port on the falling edge and is clocked out of the once serial port on the rising edge.) the debug serial clock frequency must be no greater than 1 / 8 of the processor clock frequency. when switching from input to output, the signal is tri-stated. when it is an output, this signal works with the os0 signal to provide information about the chip status. the dsck/os1 signal is an output when the chip is not in debug mode. dso output pulled high debug serial output data contained in one of the once port controller registers is provided through the dso output signal, as specified by the last command received from the external command controller. data is always shifted out the once serial port msb first. data is clocked out of the once serial port on the rising edge of dsck. the dso signal also provides acknowledge pulses to the external command controller. when the chip enters the debug mode, the dso signal will be pulsed low to indicate (acknowledge) that the once is waiting for commands. after the once receives a read command, the dso signal will be pulsed low to indicate that the requested data is available and the once serial port is ready to receive clocks in order to deliver the data. after the once receives a write command, the dso signal will be pulsed low to indicate that the once serial port is ready to receive the data to be written; after the data is written, another acknowledge pulse will be provided.
signal/pin descriptions on-chip emulation port motorola dsp56167/d, rev. 1 1-19 preliminary dr input input debug request the debug request input (dr ) allows the user to enter the debug mode of operation from the external command controller. when dr is asserted, it causes the dsp to finish the current instruction being executed, save the instruction pipeline information, enter the debug mode, and wait for commands to be entered from the dsi line. while in debug mode, the dr signal lets the user reset the once controller by asserting it and deasserting it after receiving acknowledge. it may be necessary to reset the once controller in cases where synchronization between the once controller and external circuitry is lost. dr must be deasserted after the once port responds with an acknowledge on the dso signal and before sending the first once command. asserting dr will cause the chip to exit the stop or wait state. having dr asserted during the deassertion of reset will cause the dsp to enter debug mode. table 1-14 on-chip emulation (once) port signals (continued) signal name signal type state during reset signal description
1-20 dsp56167/d, rev. 1 motorola signal/pin descriptions on-chip emulation port preliminary
motorola dsp56167/d, rev. 1 2-1 preliminary section 2 specifications general characteristics the dsp56167 is fabricated in high-density hcmos with ttl compatible inputs and outputs. table 2-1 absolute maximum ratings (v ss = 0 v) rating symbol value unit supply voltage v dd C0.3 to +7.0 v all input voltages v in ( v ss C 0.5) to (v dd + 0.5) v current drain per pin excluding v dd and v ss i10ma storage temperature t stg C55 to +150 c caution this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss or v dd ).
2-2 dsp56167/d, rev. 1 motorola specifications general characteristics preliminary table 2-2 recommended operating conditions rating symbol value unit supply voltage v dd 4.5 to 5.5 v operating temperature range t j C40 to 105 c table 2-3 thermal characteristics for 112-pin tqfp package thermal resistance symbol value rating junction-to-ambient r q ja 38.4 c/w junction-to-case (estimated) r q jc 5.5 c/w thermal characterization parameter y jt 2.3 c/w note: 1. see discussion under design considerations, heat dissipation, page 4-1 . 2. junction-to-ambient thermal resistance is based on measurements on a horizontal, single-sided, printed circuit board per semi g38-87 in natural convection. semi is semiconductor equipment and materials international, 805 east middlefield road, mountain view, ca 94043, (415) 964-5111. 3. junction-to-case thermal resistance is based on measurements using a cold plate per semi g30-88 with the exception that the cold plate temperature is used for the case temperature.
specifications dc electrical characteristics motorola dsp56167/d, rev. 1 2-3 preliminary dc electrical characteristics table 2-4 dc electrical characteristics characteristics symbol min typ max units supply voltage v dd 4.5 5.0 5.5 v input high voltage ? extal C dc coupled C ac coupled ? reset ? moda, modb, modc ? all other inputs v ihc v ihr v ihm v ih 0.7 v dd 1.0 2.5 3.5 2.0 v dd v dd v dd v dd v dd v v v v v input low voltage ? extal C dc coupled C ac coupled ? moda, modb, modc ? all other inputs v ilc v ilc v ilm v il C0.5 C0.5 C0.5 C0.5 0.2 v dd v dd C 1 2.0 0.8 v v v input leakage current extal, reset , moda/irqa , modb/irqb , modc/irqc , br i in C1 1 m a tri-state (offCstate) input current (@ 2.4 v/0.4 v) i tsi C10 10 m a output high voltage (i oh = C10 m a) v ohc v dd C 0.1 v output high voltage (i oh = C0.4 ma) v oh 2.4 v output low voltage (i oh = 10 m a) v olc 0.1 v output low voltage (i ol = 3.2 ma) r/w i ol = 1.6 ma, open-drain hreq i ol = 6.7 ma, txd i ol = 6.7 ma v ol 0.4 v internal supply current 1 ? normal mode with codec and pll disabled ? wait mode with codec and pll disabled ? stop mode with pll and clko disabled i cci i ccw i ccs 100 11 400 ma ma m a pll current when active i ccpll 2 ma analog current ? codec enabled ? codec disabled i cca 10 75 ma m a input capacitance c in 10 pf note: 1. section 4 design considerations describes how to calculate the external supply current.
2-4 dsp56167/d, rev. 1 motorola specifications ac electrical characteristics preliminary ac electrical characteristics the timing waveforms in the ac electrical characteristics are tested with a v il maximum of 0.5 v and a v ih minimum of 2.4 v for all pins, except extal, reset , moda, modb, and modc. these pins are tested using the input levels set forth in the dc electrical characteristics. ac timing specifications that are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signals transition. dsp56167 output levels are measured with the production test machine v ol and v oh reference levels set at 0.8 v and 2.0 v, respectively. figure 2-1 signal measurement reference vih vil fall time input signal note: the midpoint is v il + (v ih C v il )/2. midpoint1 low high pulse width 90% 50% 10% rise time aa0179
specifications clock operation motorola dsp56167/d, rev. 1 2-5 preliminary clock operation the system clock must be externally supplied by connecting a square wave voltage source to extal. figure 2-2 shows the recommended connection of the external source to extal and the external filter capacitor to sfxc. figure 2-2 connecting extal and the external filter capacitor extal pll plle = 1 plle = 0 fosc id3 C id0 clko internal phase ph0 at fosc cs1 C cs0 1000 pf sxfc v dds xfc 1 0.01 m f gnd s 0.1 m f 100 k w vco lf pfd yd7 C yd0 1 nf note: 1. must be a low leakage capacitor and must be located very close to the sxfc and vdds pins. pd3 C pd0 ps = 0 ps = 1 aa0773 ? 1 to ? 256 ? 2 0 to ? 2 15 ? 2 ? 1 to ? 16
2-6 dsp56167/d, rev. 1 motorola specifications clock operation preliminary table 2-5 clock operation num characteristics symbol 60 mhz unit min max 1 frequency of operation (extal input) e f 0 60 mhz 2 instruction cycle time = 2 t c i cyc 33 ns 3 wait state = t c = 2 t ws 16.6 ns 4 extal cycle period t c 16.6 ns 5 extal rise time 1 3ns 6 extal fall time 1 3ns 7 extal width high 2,3,4 (48C52% duty cycle) t h 8 ns 8 extal width low 2,3,4 (48C52% duty cycle) t l 8 ns note: 1. rise and fall time may be relaxed to 12 ns maximum if the extal input frequency is 20 mhz. if e f is between 20 mhz and 40 mhz, rise and fall time should be 4 ns maximum. if e f is between 40 mhz and 60 mhz, rise and fall time should meet the specified value (3 ns maximum). 2. the duty cycle may be relaxed to 43C57% if the extal input frequency is 20 mhz. if the extal input frequency is between 20mhz and 40mhz, the duty cycle should be such that t h and t l are 12 ns minimum. if the extal input frequency is between 40 mhz and 60 mhz, the duty cycle should be such that t h and t l meet the specified values in the 60 mhz column (8 ns minimum). 3. t = i cyc /4 is used in the electrical characteristics. the exact length of each t is affected by the duty cycle of the external clock input. 4. duty cycles and extal widths are measured at the extal input signal midpoint when ac coupled and at v dd /2 when dc coupled. figure 2-3 external clock timing t h t l 7 8 4 2 midpoint aa0774 v ihc v ilc 90% 10% 6 5 extal
specifications phase lock loop (pll) and other clock timing motorola dsp56167/d, rev. 1 2-7 preliminary phase lock loop (pll) and other clock timing reset, stop, mode select, and interrupt timing v dd = 5.0 v 10%; t j = C40 to +115?c; c l = 50 pf + 2 ttl loads ws = number of wait states programmed into the external bus access using bcr (ws = 0C15) table 2-6 pll and other clock characteristics characteristics min max unit pll output frequency 10 maximum f 1 mhz extal input clock amplitude 1 v dd v p note: 1. maximum dsp operating frequency 2. an ac coupling capacitor is required on extal if the levels are out of the normal cmos level range (v ilc > 0.2 v dd or v ihc < 0.7 v dd ). table 2-7 reset, stop, mode select, and interrupt timing (60 mhz) num characteristics min max unit 10 reset assertion to address, data and control signals high impedance 21.0 ns 11 minimum stabilization duration 1 omr bit 6 = 0 omr bit 6 = 1 600kt 60t ns ns 12 asynchronous reset deassertion to first external address output 7 16t 18t + 15 ns 13 synchronous reset setup time from reset deassertion to rising edge of clko 5 cyc C 2 ns 14 synchronous reset delay time from clko high to the first external access 7 16t + 3 16t + 16 ns 15 mode select setup time 4.8 ns 16 mode select hold time 4.0 ns 17 edge-triggered interrupt request width 8.0 ns 18 delay from irqa , irqb , irqc assertion to external data memory access out valid caused by first interrupt instruction fetch caused by first interrupt instruction execution 11t + 3 19t + 3 ns ns 19 delay from irqa , irqb , irqc assertion to general purpose output valid caused by the execution of the first interrupt instruction 22t + 3 ns
2-8 dsp56167/d, rev. 1 motorola specifications reset, stop, mode select, and interrupt timing preliminary 20 delay from external data memory address output valid caused by first interrupt instruction execution to interrupt request deassertion for level sensitive fast interrupts 2 5t C 22 + cyc ws ns 21 delay from general-purpose output valid caused by the execution of the first interrupt instruction to irqa , irqb , irqc deassertion for level sensitive fast interruptsif 2nd interrupt instruction is: single cycle 2 two cycles cyc C 26 3cyc C 26 ns ns 22 synchronous setup time from irqa , irqb , irqc assertion to synchronous falling edge of clko 5,6 12 ns 23 falling edge of clko to first interrupt vector address out valid after synchronous recovery from wait state 3,5 27t + 3 27t + 16 ns 24 irqa width assertion to recover from stop state 4 17 ns 25 delay from irqa assertion to fetch of first instruction (exiting stop) 1,3 omr bit 6 = 0 omr bit 6 = 1 524303t + 3 47t + 3 ns ns 28 duration for level sensitive irqa assertion to cause the fetch of first irqa interrupt instruction (exiting stop) 1,3 omr bit 6 = 0 omr bit 6 = 1 524303t 47t ns ns 29 delay from level sensitive irqa assertion to first interrupt vector address out valid (exiting stop) 1,3 omr bit 6 = 0 omr bit 6 = 1 524303t + 3 47t + 3 ns ns 30 dr asserted to clk low (setup time for synchronous recovery from wait state) 8 cyc+8 ns 31 clk low to dso (ack ) valid (enter debug mode) after synchronous recovery from wait state 18cyc ns 32 dr to dso (ack ) valid (enter debug mode) after asynchronous recovery from stop mode after asynchronous recovery from wait mode 29cyc 18cyc ns ns 33 dr assertion width recovery from wait/stop without entering debug short wakeup from wait/stop and enter debug long wakeup from stop enter debug 10 29cyc 262157cyc 10cyc ns ns ns table 2-7 reset, stop, mode select, and interrupt timing (60 mhz) (continued) num characteristics min max unit
specifications reset, stop, mode select, and interrupt timing motorola dsp56167/d, rev. 1 2-9 preliminary note: 1. circuit stabilization delay is required during reset when using an external clock in two cases: ? after power-on reset, and ? when recovering from stop mode. 2. when using fast interrupts and irqa and irqb are defined as level-sensitive, then timings 20 and 21 apply to prevent multiple interrupt service. to avoid these timing restrictions, the deasserted edge-triggered mode is recommended when using fast interrupt. long interrupts are recommended when using level-sensitive mode. 3. the interrupt instruction fetch is visible on the pins only in mode 3. 4. the minimum is specified for the duration of an edge triggered irqa interrupt required to recover from the stop state. this is not the minimum required so that the irqa interrupt is accepted. 5. timing 22 is for all irqx interrupts while timing #23 is only when exiting the wait state 6. timing 22 triggers off t1 in the normal state and off phi1 when exiting the wait state. 7. the instruction fetch is visible on the pins only in mode 2 and mode 3. figure 2-4 asynchronous reset timing figure 2-5 synchronous reset timing table 2-7 reset, stop, mode select, and interrupt timing (60 mhz) (continued) num characteristics min max unit v ihr first fetch 11 12 10 reset d0Cd15 a0Ca15 ps/ds r/w , bs peren aa0775 13 clko reset a0Ca15, ps/ds bs , r/w 14 peren aa0776
2-10 dsp56167/d, rev. 1 motorola specifications reset, stop, mode select, and interrupt timing preliminary figure 2-6 operating mode select timing figure 2-7 external interrupt timing (negative edge-triggered) figure 2-8 external level-sensitive fast interrupt timing v ihm v ilm v ih v il v ihr 15 reset moda, modb modc irqa , irqb , irqc 16 aa0777 irqa , irqb nmi 17 aa0778 first interrupt instruction execution/fetch a) first interrupt instruction execution b) general purpose i/o a0Ca15 irqa irqb irqc general purpose i/o irqa irqb nmi 20 18 19 21 ps/ds bs , r/w peren aa0779
specifications reset, stop, mode select, and interrupt timing motorola dsp56167/d, rev. 1 2-11 preliminary figure 2-9 synchronous interrupt from wait state timing figure 2-10 recovery from stop state using asynchronous interrupt timing figure 2-11 recovery from stop state using irqa interrupt service t0, t2 t1, t3 22 23 clko irqa , irqb nmi a0Ca15 ps/ds bs , r/w peren first interrupt instruction fetch aa0780 first instruction fetch not irqa interrupt vector irqa a0Ca15 24 25 ps/ds bs , r/w peren aa0781 irqa a0Ca15 ps/ds bs , r/w peren first irqa interrupt instruction fetch 28 aa0782 29
2-12 dsp56167/d, rev. 1 motorola specifications reset, stop, mode select, and interrupt timing preliminary figure 2-12 recovery from wait state using dr synchronous timing ? figure 2-13 recovery from wait/stop state using dr asynchronous timing t0, t2 t1, t3 clko (output) dr (input) dso (output) 33 aa0783 30 31 dr (input) dso (output) aa0784 33 32
specifications external bus synchronous timing motorola dsp56167/d, rev. 1 2-13 preliminary external bus synchronous timing v dd = 5.0 v 10%; t j = C40 to +115?c; c l = 50 pf + 1 ttl load capacitance derating : the dsp56167 external bus timing specifications are designed and tested at the maximum capacitive load of 50 pf, including stray capacitance. typically, the drive capability of the external bus pins (a0Ca15, d0Cd15, ps/ds , rd , wr , bs , peren ) derates linearly at 1 ns per 12 pf of additional capacitance from 50 pf to 250 pf of loading. port b and c pins (hi, ssi, and timer) derate linearly at 1 ns per 5 pf of additional capacitance from 50 pf to 250 pf of loading. when an internal memory access follows an external memory access, the ps/ds , r/w , rd , wr , bs , and peren strobes remain deasserted and a0Ca15 do not change from their previous state. table 2-8 external bus synchronous timing num characteristics 60 mhz unit min max 34 clk in (extal) high to clko high 2.2 10.0 ns 35 clko high to a. a0Ca15 valid b. ps/ds , peren assertion, r/w valid c. bs assertion d. rd assertion 4.0 4.0 4.0 4.0 ns ns ns ns 36 bs width deassertion 14.6 ns 37 clko high to wr assertion low t + 4.0 t + 6.0 ns 40 clko high to bs deassertion 7.4 ns 41 a.ta assertion to clko high (setup) b.ta deassertion to clko high (setup) 6.5 6.5 ns ns 42 a. clko high to ta assertion (hold) b. clko high to ta deassertion (hold) 2.0 2.0 ns ns 43 clko high to d0Cd15 out valid 4.0 ns 44 clko high to d0Cd15 out invalid (hold) 4.0 ns 45 d0Cd15 in valid to clko low (setup) 4.0 ns 46 clko low to d0Cd15 in invalid (hold) 0.0 ns 47 clko low to a. wr deassertion b. rd deassertion 3.0 3.0 ns ns 48 a. wr hold time from clko low b. rd hold time from clko low 1.0 1.0 ns ns 49 clko high to d0Cd15 tri-stated 8.0 ns 50 clko high to d0Cd15 out active 0 ns 51 clko high to a. a0Ca15 invalid b. ps/ds , peren , r/w invalid 0 0 ns ns
2-14 dsp56167/d, rev. 1 motorola specifications external bus synchronous timing preliminary figure 2-14 external bus synchronous timingno wait states data in data out note: during read-modify-write instructions and internal instructions, the address lines do not change state. t0 t1 t2 t3 t0 t1 t2 t3 t0 extal (input) clko (output) a0Ca15, ps/ds ,r/w peren note 1 bs (output) wr (output) rd (output) ta (input) d0Cd15 (output) d0Cd15 (input) 35 34 36 40 35 37 48 47 35 41 42 48 47 51 41 44 43 49 50 45 46 aa0785
specifications external bus synchronous timing motorola dsp56167/d, rev. 1 2-15 preliminary figure 2-15 external bus synchronous timingtwo wait states data in data out t0 t1 t2 tw t2 tw t2 t3 t0 extal (input) clko (output) a0Ca15, ps/ds ,r/w peren note 1 bs (output) wr (output) rd (output) ta (input) d0Cd15 (output) d0Cd15 (input) 35 34 36 40 35 37 35 41 48 51 49 43 45 50 46 aa0786 42 47 48 47 42 44 41
2-16 dsp56167/d, rev. 1 motorola specifications external bus asynchronous timing preliminary external bus asynchronous timing v dd = 5.0 v 10%; tj = C40 to +115?c; cl = 50 pf + 1 ttl load cyc = clock cycle = 1/2 instruction cycle = 2 t cycles ws = number of wait states, as determined by bcr (ws = 0 to 31) wt = ws cyc = 2t ws table 2-9 external bus asynchronous timing no. characteristics 60 mhz unit min max 52 wr and rd deassertion high to bs assertion low (two successive bus cycles) 14 ns 53 address valid to wr assertion 6.4 ns 54 wr width assertion 12.5 ns 55 wr deassertion to r/w , address invalid 3.3 ns 56 wr assertion to d0Cd15 out valid 10.4 ns 57 data out hold time from wr deassertion 4.0 ns 58 data out set up time to wr deassertion a. ws = 0 b. ws > 0 5.0 wt + t C 3.3 ns ns 59 rd deassertion to address not valid 4.0 ns 60 address valid to rd deassertion 22.1 ns 62 rd assertion width a. ws = 0 b. ws > 0 18 wt + 3t C 7 ns ns 63 address valid to input data valid a. ws = 0 b. ws > 0 22 wt + 3t C 5 ns ns 64 address valid to rd assertion 2.0 ns 65 rd assertion to input data valid 18.6 ns 66 wr deassertion to rd assertion 6.8 ns 67 rd deassertion to rd assertion 8.5 ns 68 wr deassertion to wr assertion 13.1 ns 69 rd deassertion to wr assertion 16.0 ns
specifications external bus asynchronous timing motorola dsp56167/d, rev. 1 2-17 preliminary figure 2-16 external bus asynchronous timing note: during read-modify-write instructions and internal instructions, the address lines do not change state. a0Ca15, ps/ds , r/w peren rd wr d0Cd15 bs 60 aa0787 62 67 54 68 55 66 52 69 63 58 65 57 56 53 52 59 64 data in data out
2-18 dsp56167/d, rev. 1 motorola specifications bus arbitration timingslave mode preliminary bus arbitration timingslave mode v dd = 5.0 v 10%; tj = C40 to +115?c; cl = 50 pf + 1 ttl load cyc = clock cycle = 1/2 instruction cycle = 2 t cycles ws = number of wait states for x or p external memory, determined by bcr or bcr2 (ws = 0 to 31) wt = ws cyc = 2t ws w x = number of wait states for x external memory, determined by bcr or bcr2 (ws = 0 to 31) w p = number of wait states for p external memory, determined by bcr (ws = 0 to 31) table 2-10 slave mode bus arbitration timing no. characteristics 60 mhz unit min max 70 br input to clko low setup time 2.8 ns 71 delay from br input assertion to bg output assertion no external access by the dsp external read or write access external read-modify-write access stop modeexternal bus released and bg asserted wait mode 25 5t + 6.6 3t + 6.6 5t + 6.6 t+6.6 9t +3.1 9t+wt+3.1 26t+ 4t x w x + 2t x w p + 2.7 3t + 2.7 ns 72 clko high to bg output assertion 10.2 ns 73 bg output deassertion duration for two consecutive br no external access by the dsp external read or write access external read-modify-write access stop modeexternal bus released and bg asserted wait mode external dsp accesses pending 5t + 3.7 5t + 3.7 5t + 3.4 2t + 3.3 3t + 3.4 ns ns ns ns ns 74 clko high to control bus high impedance 8.0 ns 75 clko high to bb output deassertion 7.0 ns 76 clko high to bb output (tri-stated) 18.0 ns 77 br input deassertion to bg output deassertion 8.5 ns 78 clko high to bg deassertion 15.0 ns 79 clko high to bb output active 1.0 ns 80 clko high to bb output assertion 9.4 ns 81 clko high to address and control bus active 1.0 ns 82 clko high to address and control bus valid 9.7 ns
specifications bus arbitration timingslave mode motorola dsp56167/d, rev. 1 2-19 preliminary 83 br assertion to bb deassertion no external access by the dsp external read or write access external read-modify-write access stop modeexternal bus released and bg asserted wait mode 9t + 3.1 9t + wt + 3.1 26t + 4t w x + 2t w p + 2.7 3t + 2.7 ns ns ns ns 84 br assertion to address/data/control lines tri-stated no external access by the dsp external read or write access external read-modify-write access stop modeexternal bus released and bg asserted wait mode 9t + 8.0 9t + wt + 8.0 26t + 4t w x + 2t w p + 2.7 3t + 2.7 ns ns ns ns table 2-10 slave mode bus arbitration timing (continued) no. characteristics 60 mhz unit min max
2-20 dsp56167/d, rev. 1 motorola specifications bus arbitration timingslave mode preliminary figure 2-17 external bus arbitration bus release timingslave mode clko (output) br (input) bg (output) bb (i/o) a0Ca15, ps/ds r/w peren d0Cd15 70 71 72 73 75 83 76 84 74 84 74 aa0788
specifications bus arbitration timingslave mode motorola dsp56167/d, rev. 1 2-21 preliminary figure 2-18 external bus arbitration bus acquisition timingslave mode aa0789 clko (output) br (input) bg (output) bb (i/o) a0Ca15, ps/ds r/w peren 70 77 78 79 80 82 80
2-22 dsp56167/d, rev. 1 motorola specifications bus arbitration timingmaster mode preliminary bus arbitration timingmaster mode v dd = 5.0 v 10%; tj = C40 to +115?c; cl = 50 pf + 1 ttl load table 2-11 master mode bus arbitration timing no. characteristics 60 mhz unit min max 85 clko high to br output valid 9.0 ns 86 bg input valid to clko low (setup) 1.9 ns 87 clko low to bg input deassertion (hold) 2.0 ns 88 bb input deassertion to clko low (setup) 2.0 ns 89 clko low to bb input deassertion (hold) 2.0 ns 90 clko high to bb output assertion 11.4 ns 91 clko low to bg input assertion no external access by the dsp external read or write access 3 ns ns 92 bg deassertion to bb deassertion no external access by the dsp external read or write access external read-modify-write-access stop mode - external bus released and bg asserted wait mode 48.3 64.9 ns ns ns ns ns 93 bg deassertion to address/data/control lines tri-stated no external access by the dsp external read or write access external read-modify-write-access stop mode - external bus released and bg asserted wait mode 53.3 69.9 ns ns ns ns ns
specifications bus arbitration timingmaster mode motorola dsp56167/d, rev. 1 2-23 preliminary figure 2-19 external bus arbitration bus acquisition timingmaster mode figure 2-20 external bus arbitration bus release timingmaster mode tri-state aa0790 clko (output) br (output) bg (input) bb (i/o) a0Ca15, ps/ds r/w peren 85 87 86 88 89 90 82 81 clko (output) br (output) bg (input) bb (i/o) d0Cd15, ps/ds , bs , r/w , rd , wr , 85 75 92 76 93 aa0791 91 86 74 a0Ca15, peren output
2-24 dsp56167/d, rev. 1 motorola specifications host i/o (hi) timing preliminary host i/o (hi) timing v dd = 5.0 v 10%; t j = C40 to +115?c; c l = 50 pf + 1 ttl load t = i cyc / 4 cyc = clock cycle = 1/2 instruction cycle = 2 t cycle t hsdl = host synchronization time delay t suh = host processor data setup time note: active low lines should be pulled up in a manner consistent with the ac and dc specifications. table 2-12 host i/o timing num characteristics min max unit 100 host synchronous delay 1 t3tns 101 hen /hack assertion width a. cvr,icr, isr read 2,4 b. read c. write 2t + 30 25 27 ns ns ns 102 hen /hack deassertion width 2 27 ns 103 minimum cycle time between two hen assertions for consecutive cvr, icr, isr reads 4t + 30 ns 104 host data input setup time before hen /hack deassertion 3 ns 105 host data input hold time after hen /hack deassertion 9 ns 106 hen /hack assertion to output data active from tri-state 24 ns 107 hen /hack assertion to output data valid 24 ns 108 hen /hack deassertion to output data tri-stated 17 ns 109 output data hold time after hen /hack deassertion 5 ns 110 hr/w low setup time before hen assertion 4 ns 111 hr/w low hold time after hen deassertion 4 ns 112 hr/w high setup time to hen assertion 4 ns 113 hr/w high hold time after hen /hack deassertion 3 ns 114 ha0Cha2 setup time before hen assertion 0 ns 115 ha0Cha2 hold time after hen deassertion 6 ns 116 dma hack assertion to hreq deassertion 3 6 2t + 35 ns 117 dma hack deassertion to hreq assertion 3 for dma rxl read for dma txl write for all other cases t hsdl + 3t + 4 t hsdl + 2t + 4 4 ns ns ns
specifications host i/o (hi) timing motorola dsp56167/d, rev. 1 2-25 preliminary 118 delay from hen deassertion to hreq assertion for rxl read 3 t hsdl + 3t + 4 ns 119 delay from hen deassertion to hreq assertion for txl write 3 t hsdl + 2t + 4 ns 120 delay from hen assertion to hreq deassertion for rxl read, txl write 3 13.7 2t + 16.4 ns note: 1. host synchronization delay (t hsdl ) is the time period required for the dsp56167 to sample any external asynchronous input signal, determine whether it is high or low, and synchronize it to the internal clock. 2. see host port considerations in the section on design considerations . 3. hreq is pulled up by 1 k w . 4. only if two consecutive reads from one of these registers are executed figure 2-21 host synchronization delay figure 2-22 host interrupt vector register (ivr) read table 2-12 host i/o timing (continued) num characteristics min max unit 100 aa0792 external internal 100 hreq (output) hack (input) hr/w (input) h0Ch7 (output) 101 aa0793 102 112 113 108 107 106 109 103 data valid
2-26 dsp56167/d, rev. 1 motorola specifications host i/o (hi) timing preliminary figure 2-23 host read cycle (non-dma mode) figure 2-24 host write cycle (non-dma mode) hreq (output) hen (input) ha2Cha0 (input) hr/w (input) h0Ch7 (output) 120 aa0794 data valid data valid data valid 118 103 101 102 114 115 112 113 107 108 109 106 rxl read rxh read address valid address valid address valid hreq (output) hen (input) ha2Cha0 (input) hr/w (input) h0Ch7 (input) 120 aa0795 data valid data valid data valid 119 103 101 102 114 115 110 111 105 104 txl write txh write address valid address valid address valid
specifications host i/o (hi) timing motorola dsp56167/d, rev. 1 2-27 preliminary figure 2-25 host dma read cycle figure 2-26 host dma write cycle hreq (output) hac k (input) h0Ch7 (output) data valid data valid data valid 101 102 107 108 109 106 rxl read rxh read aa0796 117 116 hreq (output) hac k (input) h0Ch7 (input) 117 101 102 104 105 txl write txh write aa0797 116 data valid data valid data valid
2-28 dsp56167/d, rev. 1 motorola specifications codec analog i/o characteristics preliminary codec analog i/o characteristics v dda = 5.0 v 10%; t j = C40 to +115?c table 2-13 codec analog i/o characteristics characteristic min typ max unit input impedance of mic and aux when selected as the a/d input: C6 db, mgs[1:0] = 00 0 db, mgs[1:0] = 01 6 db, mgs[1:0] = 10 17 db, mgs[1:0] = 11 60 45 30 30 100 75 50 50 140 105 70 70 k w k w k w k w input impedance of mic and aux when not selected as the a/d input 100 140 k w maximum source or sink current of mic or aux when not selected as the a/d input 24 m a input capacitance on mic and aux 10 pf peak input voltage on the mic/aux input for full scale linearity at v dda = 5.000 v: C6 db, mgs[1:0] = 00 0 db 1 , mgs[1:0] = 01 6 db, mgs[1:0] = 10 17 db, mgs[1:0] = 11 1.414 0.707 0.354 0.100 v p v p v p v p absolute gain variation due to v dda variation for all a/d and d/a gain settings (0.83 db due to 10% variation on v dda ) g C 0.92 g g + 0.83 db a/d absolute gain variation due to internal circuitry for all a/d gain settings (variation from ideal vrad of 0.5 v dda ) g C 1.49 g g + 1.27 db d/a absolute gain variation due to internal circuitry for all d/a gain settings (variation from ideal vrda of 0.5 v dda ) g C 1.39 g g + 1.20 db vrda and vrad output voltage plus offset (assumes no leakage current on the vdiv pin and vdda = 5.000 v) 2.500 0.010 2.500 0.050 v spkp, spkm, vrda, and vrad output current 350 m a vdiv ac input impedance 42.5 k w vdiv i/o voltage plus offset (assumes there is not leakage current on the i/o and v dda = 5.000 v) 2.500 0.005 2.500 0.025 v differential dc offset between spkp and spkm 50 mv single-ended dc offset of spkp and spkm with respect to vrda 100 mv
specifications codec analog i/o characteristics motorola dsp56167/d, rev. 1 2-29 preliminary a/d output dc offset (assuming input is at vrad): C6 db, mgs[1:0] = 00 0 db, mgs[1:0] = 01 6 db, mgs[1:0] = 10 17 db, mgs[1:0] = 11 $ff00 $fe00 $fc00 $f800 $0000 $0000 $0000 $0000 $0100 $0200 $0400 $0800 allowable differential load capacitance between spkp and spkm (with 3 k w in series, 4 khz maximum frequency) 15nf allowable single-ended load capacitance on spkp and spkm (with 1.5 k w in series, 4 khz maximum frequency) 2 30nf allowable single-ended shunt capacitance to ground 50pf allowable differential shunt capacitance 25 pf maximum linear range of single-ended signal output level at vdda = 5.000 v: C15 db, vc[3:0] = 0000 C10 db, vc[3:0] = 0001 C5 db, vc[3:0] = 0010 0 db 3 , vc[3:0] = 0011 5C40 db, vc[3:0] > 0011 0.125 0.223 0.397 0.707 1.000 v p v p v p v p v p maximum linear range of single-ended signal output level at vdda = 5.000 v: C15 db, vc[3:0] = 0000 C10 db, vc[3:0] = 0001 C5 db, vc[3:0] = 0010 0 db 3 , vc[3:0] = 0011 5C40 db, vc[3:0] > 0011 0.250 0.446 0.794 1.414 2.000 v p v p v p v p v p single-ended load resistance (referenced from 0.5 v dda ) 2.8 k w differential load resistance 5.6 k w output impedance of spkp and spkm at 0 hz to 4 khz 50 w output impedance of spkp and spkm during power down 140 200 280 k w output transition time of spkp and spkm from codec power up condition 4 15 m s note: 1. 0 dbm0 corresponds to 3.00 db below the input saturation level of 1.0 v p with v dda = 5.0 v. 2. ac coupling is necessary in single-ended mode when the load resistor is not tied to vrda. 3. 0 dbm0 corresponds to 3.00 db below the output saturation level of 1.0 v p single-ended with v dda = 5.0 v. 4. during power down and during the first 15 m s after a power up event, the maximum current loading for spkp and spkm pins is 1.0 m a. table 2-13 codec analog i/o characteristics (continued) characteristic min typ max unit
2-30 dsp56167/d, rev. 1 motorola specifications codec a/d and d/a performance preliminary codec a/d and d/a performance v dda = 5.0 v 10%; t j = C40 to +115?c table 2-14 codec performance levels characteristic input signal level min. typical 1 max. unit a/d signal-to-noise plus distortion ratio s /( n + thd) 0 dbm0 55 65 db C50 dbm0 15 20 db d/a signal-to-noise plus distortion ratio s / (n + thd) 0 db 55 60 db C50 db 15 15 db note: 1. 0 db gain on the a/d and d/a; codec clock at 2.048 mhz with 128 decimation/interpolation ratio 2. 0 dbm0 corresponds to 3.00 db below the input saturation level of 1.0 v p single-ended with v dda = 5.0 v. figure 2-27 an example of s/n and s/(n + thd) performance for the codec a/d section s in db db 0 10 20 30 40 50 60 70 80 0 -2.86 -5.85 -8.84 -11.85 -14.85 -17.85 -20.86 -23.86 -26.85 -29.89 -32.85 -35.84 -38.85 -41.85 -44.85 -47.8 -50.81 -53.77 -56.76 59.76 -62.83 -65.67 -68.79 -71.91 -74.58 -77.91 s/n s/(n+thd) input signal in db aa0900
specifications other on-chip codec characteristics motorola dsp56167/d, rev. 1 2-31 preliminary other on-chip codec characteristics v dd = 5.0 v 10%; t j = C40 to +115?c; c l = 50 pf + 1 ttl load table 2-15 codec i/o device characteristics characteristic min. typical max. unit codec master clock 1 2.048 3 mhz codec sampling rate 7812 16000 46150 hz a/d section group delay 0.06 0.17 0.40 ms d/a section group delay 0.07 0.17 0.37 ms
2-32 dsp56167/d, rev. 1 motorola specifications 16-bit synchronous serial interface (ssi) timing preliminary 16-bit synchronous serial interface (ssi) timing v dd = 5.0 v 10%; t j = C40 to +115?c; c l = 50 pf + 1 ttl load t = i cyc / 4 sck = serial clock sfs = transmit/receive frame sync i ck = internal clock and frame sync x ck = external clock and frame sync bl = bit length wl = word length t s = sck/2 note: all the timings for the 16-bit ssi are given for a non-inverted serial clock polarity (sckp = 0 in crb) and a non-inverted frame sync (fsi = 0 in crb). if the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal sck and/or the frame sync sfs in the tables and in the figures. table 2-16 ssi timing num characteristics 60 mhz case unit min max 134 sck rising edge to sfs in (bl) high 20.4 i ck ns 135 sck rising edge to sfs in (bl) low 16.7 i ck ns 136 sck rising edge to sfs in (wl) high 20.4 i ck ns 137 sck rising edge to sfs in (wl) low t s 2 i ck ns 138 data in setup time before sck falling edge 3.0 i ck ns 139 data in hold time after sck falling edge 8.5 i ck ns 140 sck rising edge to sfs out (bl) high 21 i ck ns 141 sck rising edge to sfs out (wl) high 16.0 i ck ns 142 sck rising edge to sfs out low 20.4 i ck ns 143 sck rising edge to data out enable from high impedance 1.2 i ck ns 144 sck rising edge to data out valid 10 i ck ns 145 sck rising edge to data out invalid 16.7 i ck ns 146 sck rising edge to data out high impedance 16.7 i ck ns 150 sck clock cycle 1 27 x ck ns 153 sck clock rise/fall time 10 x ck ns 154 sck rising edge to sfs out (bl) high 3.3 x ck ns 155 sck rising edge to sfs out (bl) low 6 x ck ns
specifications 16-bit synchronous serial interface (ssi) timing motorola dsp56167/d, rev. 1 2-33 preliminary 156 sck rising edge to sfs out (wl) high 20.5 x ck ns 157 sck rising edge to sfs out (wl) low 35.0 x ck ns 158 data in setup time before sck falling edge 7 x ck ns 159 data in hold time after sck falling edge 13.2 x ck ns 160 sck rising edge to sfs in (bl) high 26.1 x ck ns 161 sck rising edge to sfs in (bl) low 13.0 x ck ns 162 sck rising edge to sfs in (wl) high 30 x ck ns 163 sck rising edge to data out enable from high impedance 7.5 x ck ns 164 sck rising edge to data out valid 20.5 x ck ns 165 sck rising edge to data out invalid 10.4 x ck ns 166 sck rising edge to data out high impedance 19.7 x ck ns note: 1. for internal clock, external clock cycle is defined by i cyc and ssi control register. table 2-16 ssi timing (continued) num characteristics 60 mhz case unit min max
2-34 dsp56167/d, rev. 1 motorola specifications 16-bit synchronous serial interface (ssi) timing preliminary figure 2-28 ssi internal clock timing sck continuous (output) sck gated (output) sfs (bit early) (input) sfs (word early) (input) sfs (bit) (input) sfs (word) (input) std (output) srd (input) sfs (bit early) (output) sfs (word early) (output) sfs (bit) (output) sfs (word) (output) 137 135 135 134 136 143 144 138 139 140 141 142 142 142 141 137 146 145 134 136 142 140 aa0801
specifications 16-bit synchronous serial interface (ssi) timing motorola dsp56167/d, rev. 1 2-35 preliminary figure 2-29 ssi external clock timing sck continuous (input) sck gated (input) sfs (bit early) (output) sfs (word early) (output) sfs (bit) (output) sfs (word) (output) std (output) srd (input) sfs (bit early) (input) sfs (word early) (input) sfs (bit) (input) sfs (word) (input) 153 157 155 155 154 156 163 164 158 159 160 161 162 162 162 161 157 166 165 154 156 162 160 aa0802 150
2-36 dsp56167/d, rev. 1 motorola specifications timer timing preliminary timer timing v dd = 5.0 v 10%; t j = C40 to +115?c; c l = 50 pf + 1 ttl load table 2-17 timer timing (60 mhz) num characteristics min max unit 170 tin valid to clko low (setup time) 8 ns 171 clko low to tin invalid (hold time) 0 8.0 ns 172 clko high to tout asserted 3.5 14.0 ns 173 clko high to tout deasserted 0 ns 174 tin period 8t ns 175 tin high/low period 4t ns figure 2-30 timer timing aa0803 clko (output) tin (input) tout (output) 170 172 173 171
specifications gpio timing motorola dsp56167/d, rev. 1 2-37 preliminary gpio timing v dd = 5.0 v 10%; t j = C40 to +115?c; c l = 50 pf + 1 ttl load table 2-18 gpio timing num characteristics min max unit 201 clko edge to gpio output valid (gpio output delay time) 19.7 ns 202 clko edge to gpio output not valid (gpio output hold time) 0 ns 203 gpio input valid to clko edge (gpio input setup time) 10.0 ns 204 clko edge to gpio input not valid (gpio input hold time) 4.0 ns figure 2-31 gpio timing valid clko (output) gpio (output) gpio (input) 201 202 204 203 aa0804
2-38 dsp56167/d, rev. 1 motorola specifications once port timing preliminary once port timing v dd = 5.0 v 10%; t j = C40 to +115?c; c l = 50 pf + 1 ttl load table 2-19 once port timing num characteristics min max unit 180 dsck high to dso valid 27.6 ns 181 dsi valid to dsck low (setup) 15 ns 182 dsck low to dsi invalid (hold) 5 ns 183 dsck high 1 33 ns 184 dsck low 1 2t c ns 185 dsck cycle time 1 4t c ns 186 clko high to os0Cos1 valid 14.5 ns 187 clko high to os0Cos1 invalid 21.7 ns 188 last dsck high to os0Cos1 2 last dsck high to ack active (data) 2 last dsck high to ack active (command) 2 10t + t d +14.5 10t + t d +13.5 21t + t d +13.5 ns ns ns 190 dso (ack ) asserted to first dsck high 3t c ns 191 dso (ack ) width asserted: a. when entering debug mode b. when acknowledging command/data transfer 34 51 ns ns 192 last dsck low of read register to first dsck high of next command 6t c ns 193 dsck high to dso invalid 2 7ns 194 dr asserted to dso (ack ) asserted 19.4 ns note: 1. 45C55% duty cycle 2. t d = dsck high (timing number 183) figure 2-32 once serial clock timing dsck (input) 184 183 185 aa0805
specifications once port timing motorola dsp56167/d, rev. 1 2-39 preliminary figure 2-33 once acknowledge timing figure 2-34 once data i/o to status timing figure 2-35 once data i/o to status timing dr (input) dso (output) (ack ) 194 aa0806 note: 1. tri-state, external pull-down resistor dsck (input) dso (output) dsi (input) 188 181 aa0807 182 180 193 (last) note 1 (os1) (ack ) (os0) note 1: tri-stated, external pull-down resistor os1 (output) dso (output) os0 (output) 180 aa0808 181 191 182 190 (dsck input) (dso output) (dsi input)
2-40 dsp56167/d, rev. 1 motorola specifications once port timing preliminary figure 2-36 once data i/o to status timing figure 2-37 once clock to status timing figure 2-38 once dsck next command after read register timing note: high impedance, external pull-down resistor (dsck input) (dso output) (dsi input) os1 (output) dso (output) os0 (output) (see note) (see note) 239 241 240 241 236 237 aa0503 clko (output) os0C1 (output) 187 186 aa0809 192 aa0810 dsck (input) (read register) (next command)
motorola dsp56167/d, rev. 1 3-1 preliminary section 3 packaging pin-out and package information top and bottom views of the tqfp package are shown in figure 3-1 and figure 3-2 with their pin-outs.
3-2 dsp56167/d, rev. 1 motorola packaging pin-out and package information preliminary figure 3-1 top view of the 112-pin plastic (fv) thin quad flat package v ssa/d d2 d3 v dda/d d4 d5 v ssa/d d6 d7 d8 d9 v ssa/d d10 d11 v dda/d d12 d13 v ssa/d d14 d15 ta dr v dda spkp spkm v ssa vdiv vrda orientation mark 1 29 57 85 d1 d0 a15 a14 v ssa/d a13 a12 a11 v ssq v dda/d a10 v ssa/d a9 a8 a7 a6 v ddq v ssa/d a5 a4 v dda/d a3 a2 v ssa/d a1 a0 modc/irqc modb/irqb mic aux vrad bg v ddq br bb v ddc wr v ssc rd ps/ds bs r/w dso dsck/os1 dsi/os0 clko v ssq v sss sxfc v dds extal sfs1/pc9 v sspb peren sck1/pc7 h7/pb7 (top view) moda/irqa reset std0/pc0 srd0/pc1 sck0/pc2 v sspc sfs0/pc4 tin/pc10 v ddpc tout/pc11 ha0/pb8 v sspc ha1/pb9 ha2/pb10 hr/w /pb11 hen /pb12 hack /pb14 hreq /pb13 h0/pb0 h1/pb1 std1/pc5 srd1/pc6 h4/pb4 h3/pb3 h2/pb2 v ddpb h5/pb5 h6/pb6 note: an overbar indicates the signal is asserted when the voltage = ground (active low). aa0811
packaging pin-out and package information motorola dsp56167/d, rev. 1 3-3 preliminary figure 3-2 bottom view of the112-pin plastic (fv) thin quad flat package moda/irqa reset std0/pc0 srd0/pc1 sck0/pc2 v sspc sfs0/pc4 tin/pc10 v ddpc tout/pc11 ha0/pb8 v sspc ha1/pb9 ha2/pb10 hr/w /pb11 hen /pb12 hack /pb14 hreq /pb13 h0/pb0 h1/pb1 std1/pc5 srd1/pc6 h4/pb4 h3/pb3 h2/pb2 v ddpb h5/pb5 h6/pb6 v ssa/d d2 d3 v dda/d d4 d5 v ssa/d d6 d7 d8 d9 v ssa/d d10 d11 v dda/d d12 d13 v ssa/d d14 d15 ta dr v dda spkp spkm v ssa vdiv vrda orientation mark 1 29 57 85 h7/pb7 sck1/pc7 peren v sspb sfs1/pc9 extal v dds sxfc v sss v ssq clko dsi/os0 dsck/os1 dso r/w bs ps/ds rd v ssc wr v ddc bb br v ddq bg vrad aux mic modb/irqb modc/irqc a0 a1 v ssa/d a2 a3 v dda/d a4 a5 v ssa/d v ddq a6 a7 a8 a9 v ssa/d a10 v dda/d v ssq a11 a12 a13 v ssa/d a14 a15 d0 d1 (on top side) (bottom view) note: an overbar indicates the signal is asserted when the voltage = ground (active low). aa0812
3-4 dsp56167/d, rev. 1 motorola packaging pin-out and package information preliminary the dsp56167 signals that may be programmed as general purpose i/o are listed with their primary function in table 3-1 . table 3-1 dsp56167 general purpose i/o pin identification pin number primary function port gpio id 66 h0 b pb0 65 h1 pb1 60 h2 pb2 61 h3 pb3 62 h4 pb4 58 h5 pb5 57 h6 pb6 56 h7 pb7 74 ha0 pb8 72 ha1 pb9 71 ha2 pb10 70 hr/w pb11 69 hen pb12 67 hreq pb13 68 hack pb14 82 std0 c pc0 81 srd0 pc1 80 sck0 pc2 78 sfs0 pc4 64 std1 pc5 63 srd1 pc6 55 sck1 pc7 52 sfs1 pc9 77 tin pc10 75 tout pc11
packaging pin-out and package information motorola dsp56167/d, rev. 1 3-5 preliminary table 3-2 dsp56167 signal identification by pin number pin no. signal name pin no. signal name pin no. signal name 1v ssa/d 26 v ssa 51 extal 2 d2 27 vdiv 52 sfs1/pc9 3 d3 28 vrda 53 v sspb 4v dda/d 29 mic 54 peren 5 d4 30 aux 55 sck1/pc7 6 d5 31 vrad 56 h7/pb7 7v ssa/d 32 bg 57 h6/pb6 8d633v ddq 58 h5/pb5 9d734br 59 v ddpb 10 d8 35 bb 60 h2/pb2 11 d9 36 v ddc 61 h3/pb3 12 v ssa/d 37 wr 62 h4/pb4 13 d10 38 v ssc 63 srd1/pc6 14 d11 39 rd 64 std1/pc5 15 v dda/d 40 ps/ds 65 h1/pb1 16 d12 41 bs 66 h0/pb0 17 d13 42 r/w 67 hreq /pb13 18 v ssa/d 43 dso 68 hack /pb14 19 d14 44 dsck/os1 69 hen /pb12 20 d15 45 dsi/os0 70 hr/w /pb11 21 ta 46 clko 71 ha2/pb10 22 dr 47 v ssq 72 ha1/pb9 23 v dda 48 v sss 73 v sspc 24 spkp 49 sxfc 74 ha0/pb8 25 spkm 50 v dds 75 tout/pc11
3-6 dsp56167/d, rev. 1 motorola packaging pin-out and package information preliminary 76 v ddpc 89 v ssa/d 102 a10 77 tin/pc10 90 a2 103 v dda/d 78 sfs0/pc4 91 a3 104 v ssq 79 v sspc 92 v dda/d 105 a11 80 sck0/pc2 93 a4 106 a12 81 srd0/pc1 94 a5 107 a13 82 std0/pc0 95 v ssa/d 108 v ssa/d 83 reset 96 v ddq 109 a14 84 moda/irqa 97 a6 110 a15 85 modb/irqb 98 a7 111 d0 86 modc/irqc 99 a8 112 d1 87 a0 100 a9 88 a1 101 v ssa/d table 3-2 dsp56167 signal identification by pin number (continued) pin no. signal name pin no. signal name pin no. signal name
packaging pin-out and package information motorola dsp56167/d, rev. 1 3-7 preliminary power and ground pins have special considerations for noise immunity. see the section design considerations . table 3-3 dsp56167 power supply pins pin number power supply circuit supplied 23 v dda codec 26 v ssa 92 v dda/d address bus buffers 103 89 v ssa/d 95 101 108 4v dda/d data bus buffers 15 1v ssa/d 7 12 18 36 v ddc bus control buffers 38 v ssc 59 v ddpb port b/host interface buffers 53 v sspb 76 v ddpc port c/ssi and timer buffers 73 v sspc 79 33 v ddq internal logic 96 47 v ssq 104 50 v dds pll and clock 48 v sss
3-8 dsp56167/d, rev. 1 motorola packaging pin-out and package information preliminary figure 3-3 112-pin thin plastic quad flat pack (tqfp) mechanical information notes: 1.dimensioning and tolerancing per asme y14.5m-1994. 2.dimensions in millimeters. 3.datums l, m and n to be determined at the seating plane. datum t. 4.dimensions s and v to be determined at seating plane. datum t. 5.dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b include mold mismatch. 6.dimension d does not include dambar protrusion. allowable dambar protrusion shall not cause the d dimension to exceed 0.46 . view y l-m 0.20 n t 4x 4x 28 tips pin 1 ident 1 112 85 84 28 57 29 56 b v v1 b1 a1 s1 a s l-m 0.20 n t l n m section j1-j1 rotated 90 counterclockwise base metal j aa f d l-m m 0.13 n t view ab 0.10 t 3 q c c2 2 q 0.050 seating plane t 112x j1 view y j1 p g 108x 4x c l x x=l, m or n gage plane 1 q q view ab c1 (z) (y) e (k) r2 r1 0.25 r r dim min max millimeters a 20.000 bsc a1 10.000 bsc b 20.000 bsc b1 10.000 bsc c --- 1.600 c1 0.050 0.150 c2 1.350 1.450 d 0.270 0.370 e 0.450 0.750 f 0.270 0.330 g 0.650 bsc j 0.090 0.170 k 0.500 ref p 0.325 bsc r1 0.100 0.200 r2 0.100 0.200 s 22.000 bsc s1 11.000 bsc v 22.000 bsc v1 11.000 bsc y 0.250 ref z 1.000 ref aa 0.090 0.160 q q q q 0 ? 3 ? 11 ? 11 ? 8 ? 7 ? 13 ? 13 ? 1 2 3 case 987-01 issue a
packaging ordering drawings motorola dsp56167/d, rev. 1 3-9 preliminary ordering drawings complete mechanical information regarding dsp56167 packaging is available by facsimile through motorola's mfax? system. call the following number to obtain information by facsimile: the mfax automated system requests the following information: ? the receiving facsimile telephone number including area code or country code ? the callers personal identification number (pin) note: for first time callers, the system provides instructions for setting up a pin, which requires entry of a name and telephone number. ? the type of information requested: C instructions for using the system C a literature order form C specific part technical information or data sheets C other information described by the system messages a total of three documents may be ordered per call. the dsp56167 112-pin tqfp package mechanical drawing is referenced as 987-01. (602) 244-6591
3-10 dsp56167/d, rev. 1 motorola packaging ordering drawings preliminary
motorola dsp56167/d, rev. 1 4-1 preliminary section 4 design considerations heat dissipation an estimation of the chip junction temperature, t j , in c can be obtained from the equation: equation 1: where: t a = ambient temperature ?c r q ja = package junction-to-ambient thermal resistance ?c/w p d = power dissipation in package historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: equation 2: where: r q ja = package junction-to-ambient thermal resistance ?c/w r q jc = package junction-to-case thermal resistance ?c/w r q ca = package case-to-ambient thermal resistance ?c/w r q jc is device-related and cannot be influenced by the user. the user controls the thermal environment to change the case-to-ambient thermal resistance, r q ca . for example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or otherwise change the thermal dissipation capability of the area surrounding the device on a printed circuit board. this model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. for ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the printed circuit board, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. t j t a p d r q ja () + = r q ja r q jc r q ca + =
4-2 dsp56167/d, rev. 1 motorola design considerations heat dissipation preliminary the thermal performance of plastic packages is more dependent on the temperature of the printed circuit board (pcb) to which the package is mounted. again, if the estimations obtained from r q ja do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. a complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages: ? to minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. ? to define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. ? if the temperature of the package case (t t ) is determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (t j - t t )/p d . as noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. from a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. in natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. hence, the new thermal metric, thermal characterization parameter or y jt , has been defined to be (t j - t t )/p d . this value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface, and to errors caused by heat loss to the sensor. the recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. note: table 2-2 recommended operating conditions on page 2-2 contains the package thermal values for this chip.
design considerations electrical design considerations motorola dsp56167/d, rev. 1 4-3 preliminary electrical design considerations use the following list of recommendations to assure correct dsp operation: ? provide a low-impedance path from the board power supply to each v dd pin on the dsp. ? provide a low-impedance path from the board ground to each v ss pin. ? use at least six 0.01C0.1 m f bypass capacitors, positioned as close as possible to the four sides of the package, to connect between the v dd power source and v ss . refer to the following section analog i/o considerations for special requirements for the codec circuitry. ? ensure that capacitor leads and associated printed circuit traces that connect to the chip v dd and v ss pins are less than 0.5 inch per capacitor lead. ? use at least a four-layer pcb with two inner layers for v dd and v ss . refer to the following section analog i/o considerations for special requirements for the codec circuitry. ? because the dsp output signals have fast rise and fall times, pcb trace lengths should be less than 6 inches maximum. this recommendation particularly applies to the address and data buses, as well as the ps/ds , bs , rd , wr , r/ w , peren , irqa , irqb , irqc , hen , hr/w , and hack pins. ? when calculating capacitance, consider all device loads including parasitic capacitance due to pcb traces,. this is especially critical in systems with higher capacitive loads that could create higher transient currents in the v dd and v ss circuits. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss or v dd ).
4-4 dsp56167/d, rev. 1 motorola design considerations analog i/o considerations preliminary ? if possible, do not have digital signals running over the analog v dd and ground planes. decouple analog v dd and ground planes as close as possible to the dsp. ? do not route clock signal lines across multiple signal lines. keep the clock signals away from the analog power and ground lines and all analog signal lines. ? take special care to minimize noise levels on the pll supply pins (both v dd and v ss ). analog i/o considerations this section discusses the requirements of the on-chip codec. the two analog inputs (mic and aux) are electrically identical. when one is not used, it can be left floating. when an input is used, an ac coupling capacitor is required. the value of the capacitor combines with the input impedance of mic or aux to determine the cutoff frequency of a high pass filter. the input impedance of mic and aux varies with respect to the microphone gain select value (mgs[1:0]). an ac coupling capacitor of 10 m f defines a high pass filter pole of 3 hz. a smaller capacitor value moves this pole higher in frequency. figure 4-1 shows the recommended analog i/o and power supply configurations.
design considerations analog i/o considerations motorola dsp56167/d, rev. 1 4-5 preliminary figure 4-1 recommended analog i/o configuration vrad sd modulator 2.5 v 10% mic vrda aux C6 db 6 db mgs[1:0] sd modulator vc3Cvc0 max spkp 2 v p (1/2 v dd ) spkm (max 1 v p when single ended on 1.5 k w ) mux ins bit 17 db vdiv 3 3 k w 15 nf 85 k w 85 k w digital v dd v dda v ssa + 15 m f 0.1 m f v ssa +5 v + 220 m f analog decoupling near dsp single trace ext. gnd ext. supply gnd digital v ss single trace 0.01 m f 10 m f 600 w 0.001 m f 10 m f 600 w vrad 0.001 m f 5.6 k w vrda v ssa v dda ( 0.35 ma) + 15 m f 0.1 m f v ssa + 15 m f 0.1 m f v ssa 0.1 m f active rc + 15 m f v ssa g reconstruction filter 1-bit dac 5.6k w v dda v ssa aa0798
4-6 dsp56167/d, rev. 1 motorola design considerations analog i/o considerations preliminary figure 4-2 shows three possible output configurations. configuration a is highly recommended, because the termination impedance between spkp and spkm is matched. configurations b and c require an ac coupling capacitor because the load resistor is tied to v ssa . figure 4-3 shows a recommended layout for power and ground planes. a four-layer board is recommended. the top layer (directly under the parts) and the bottom layers should be interconnected layers. the two center layers should be power and ground. ground and power planes should be completely separated, and the digital and analog power/ground planes should not overlap. all codec pins and all codec signal traces should be over the analog planes. the analog planes should not encompass any digital pins. figure 4-2 codec output configurations figure 4-3 recommended ground and power plane layout spkp spkm 20 k w 40 k w 20 k w vrda 10 k w spkp spkm spkp spkm 0 < c 30 nf nc (a) (b) (c) C + v dda v ssa 0 < c 30 nf 0 < c 30 nf 3 1.5 k w3 1.5 k w 3 1.5 k w aa0799 1 112 85 84 57 56 29 28 digital ground and power planes analog ground and power planes
design considerations analog i/o considerations motorola dsp56167/d, rev. 1 4-7 preliminary figure 4-4 shows that 0.1 m f bypass capacitors should be located as close to the pins being bypassed as possible. connect the ground side of the bypass capacitors to v ssa by short traces. the pins requiring 0.1 m f bypass capacitors are vrda, vrad, and v dda . these pins and the vdiv pin should have bypass capacitors of the largest size practical; 10 m f should be considered a minimum size for the larger capacitors (65 m f may be used on vdiv). the capacitors should be placed near the package, but do not have to be immediately next to the pins. as shown in figure 4-5 on page 4-8, run the dac outputs (spkp and spkm) next to each other. if possible, use the output differentially. shield analog signal traces by running traces connected to the analog ground next to them. all unused board area (on both interconnect levels) should be copper-filled and connected to analog ground. for clarity and simplicity, copper fill is indicated by text, but not shown in. the adc input anti-aliasing filtering should be done with respect to vrad. figure 4-6 on page 4-9 shows four examples of good power supply connections. figure 4-4 suggested top layer bypassing 29 28 vrad aux mic v dda v ssa vdiv vrda spkp spkm 3 15 m f 0.1 m f 0.1 m f 65 m f 0.1 m f 15 m f 0.1 m f 15 m f
4-8 dsp56167/d, rev. 1 motorola design considerations analog i/o considerations preliminary figure 4-5 suggested bottom layer routing 29 28 vrad aux mic v dda v ssa vdiv vrda spkp spkm + C mic in 1 nf 1 m f 5.6 k w 10 k w 20 k w spk out 40 k w 20 k w
design considerations analog i/o considerations motorola dsp56167/d, rev. 1 4-9 preliminary figure 4-6 four possible power supply connections 29 28 vrad aux mic v dda v ssa vdiv vrda spkp spkm ideal choice two separate power supplies, one for digital and one for analog. ground planes connected with a single trace as close as possible to the v dda on the codec. 29 28 vrad aux mic v dda v ssa vdiv vrda spkp spkm voltage regulator voltage regulator second choice one power supply, two regulators, one for digital and one for analog. ground planes connected with a 10 w resistor as close as possible to the v dda on the codec. 10 w 29 28 vrad aux mic v dda v ssa vdiv vrda spkp spkm voltage regulator third choice one power supply. one regulator for the analog supply. digital supplies driven directly by voltage source. ground planes connected with a 10 w resistor as close as possible to the v dda on the codec. 10 w 29 28 vrad aux mic v dda v ssa vdiv vrda spkp spkm fourth choice one power supply. ground planes connected at source. ground planes connected with a 10 w resistor as close as possible to the v dda on the codec. 10 w
4-10 dsp56167/d, rev. 1 motorola design considerations power consumption preliminary power consumption power dissipation is a key issue in portable dsp applications. the following describes some factors which affect current consumption. current consumption is described by the formula: equation 3: where: i = current in a c = node/pin capacitance in f v = voltage swing in v f = frequency of node/pin toggle (in hz) for example, for an address pin loaded with a 50 pf capacitance and operating at 5.5 v with a 60 mhz clock, toggling at its maximum possible rate (which is 15 mhz), the current consumption is: equation 4: the maximum internal current value (i cci -max), reflects the maximum i cc expected when running a test code. this represents typical internal activity, and is included as a point of reference. some applications may consume more or less current depending on the code used. the typical internal current value (i cci -typ) reflects what is typically seen when running the given code. the following steps are recommended for applications requiring very low current consumption: 1. minimize external memory accesses; use internal memory accesses instead. 2. minimize the number of pins that are switching. 3. minimize the capacitive load on the pins. 4. connect unused digital inputs to v dd or v ss . connect unused i/o pins through 10 k w resistors to v dd or v ss . 5. all port a input pins and bidirectional pins must have a valid state at all times when port a is released to minimize power consumption; therefore the pins must be pulled up or down or driven by another device. 6. when the codec is not used, connect v dda to v dd and v ssa to v ss and decouple vrad and vard. leave all other codec pins floating. i cvf = i5010 12 C 5.5 15 10 6 4.125ma ==
design considerations pll usage considerations motorola dsp56167/d, rev. 1 4-11 preliminary pll usage considerations the pll can be used to generate the dsp core system clock. the specific operating frequency is determined by choosing the appropriate input frequency (extal) and the id, yd, and pd counter divider ratios. these ratios are defined in the pll control register 0 (pcr0), using the following formula: the best pll performance is attained when the id and yd counter values are kept in a small range to minimize lock time and jitter. a higher input frequency to the pll will result in a higher correction rate, therefore producing a more stable output clock. for example, with an input extal frequency of 10 mhz, a plcr0 value of $0317 will result in a more stable 60 mhz system clock than will a plcr0 value of $0f5f. a programming ratio of extal/(id + 1) 3 1 mhz is recommended. the external filter capacitor (xfc) is another parameter affecting lock time and stability of the pll system. this low-leakage capacitor should be connected between sxfc and gnd s , as close as possible to the pins. the pll pins (vdds, gnds, and sxfc) should be isolated, as much as possible, from any external noise, preferably in a separate ground plane. the pll modifies the voltage on the vco by varying the charge on the capacitor connected to xfc. in effect, the pll can be viewed as a second-order control system in which the sfc influences the natural frequency and damping factor for the system. if the capacitor is too small, the system will be severely underdamped and unstable, which yields a large jitter. if the capacitor is too large, the pll becomes overdamped and may not be able to adjust to voltage changes within a reasonable lock time. the pll lock detection circuitry does not require the system to be underdamped. a recommended connection diagram is shown in figure 4-7 on page 4-12. fosc yd 1 + id 1 + () 2 pd ------------------------------------ extal =
4-12 dsp56167/d, rev. 1 motorola design considerations pll usage considerations preliminary figure 4-7 connecting extal and the external filter capacitor extal pll plle = 1 plle = 0 fosc id3 C id0 clko internal phase ph0 at fosc cs1 C cs0 1000 pf sxfc v dds xfc 1 0.01 m f gnd s 0.1 m f 100 k w vco lf pfd yd7 C yd0 1 nf note: 1. must be a low leakage capacitor and must be located very close to the sxfc and vdds pins. pd3 C pd0 ps = 0 ps = 1 aa0773 ? 1 to ? 256 ? 2 0 to ? 2 15 ? 2 ? 1 to ? 16
design considerations host port usage considerations motorola dsp56167/d, rev. 1 4-13 preliminary host port usage considerations careful synchronization is required when reading multibit registers that are written by another asynchronous system. this is a common problem when two asynchronous systems are connected. the situation exists in the host port. the considerations for proper operation are discussed below. host programmer considerations ? unsynchronized reading of receive byte registers when reading receive byte registers, rxh or rxl, the host programmer should use interrupts or poll the rxdf flag which indicates that data is available. this assures that the data in the receive byte registers will be stable. ? overwriting transmit byte registers the host programmer should not write to the transmit byte registers, txh or txl, unless the txde bit is set indicating that the transmit byte registers are empty. this guarantees that the transmit byte registers will transfer valid data to the hrx register. ? synchronization of status bits from dsp to host hc, hreq, dma, hf3, hf2, trdy, txde, and rxdf (refer to dsp56167 users manual , i/o interface section, host/dma interface programming model for descriptions) status bits are set or cleared from inside the dsp and read by the host processor. the host can read these status bits very quickly without regard to the clock rate used by the dsp, but the possibility exists that the state of the bit could be changing during the read operation. this is generally not a system problem, since the bit will be read correctly in the next pass of any host polling routine. however, if the host asserts the hen for more than timing number 101 (t101), with a minimum cycle time of timing number 103 (t103), then the status is guaranteed to be stable. note: a potential problem exists when reading status bits hf3 and hf2 as an encoded pair. if the dsp changes hf3 and hf2 from 00 to 11, there is a small probability that the host could read the bits during the transition and receive 01 or 10 instead of 11. if the combination of hf3 and hf2 has significance, the host could read the wrong combination. solution: a. read the bits twice and check for consensus. b. assert hen access for t101a so that status bit transitions are stabilized.
4-14 dsp56167/d, rev. 1 motorola design considerations host port usage considerations preliminary ? overwriting the host vector the host programmer should change the host vector register only when the host command bit (hc) is clear. this change will guarantee that the dsp interrupt control logic will receive a stable vector. ? cancelling a pending host command exception the host processor may elect to clear the hc bit to cancel the host command exception request at any time before it is recognized by the dsp. because the host does not know exactly when the exception will be recognized (due to exception processing synchronization and pipeline delays), the dsp may execute the host exception after the hc bit is cleared. for these reasons, the hv bits must not be changed at the same time the hc bit is cleared. dsp programmer considerations when reading hf0 and hf1 as an encoded pair, the dma, hf1, hf0, and hcp, htde, and hrdf (refer to dsp56167 users manual , i/o interface section, host/ dma interface programming model for descriptions) status bits are set or cleared by the host processor side of the interface. these bits are individually synchronized to the dsp clock. note: a potential problem exists when reading status bits hf1 and hf2 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have significance). a very small probability exists that the dsp will read the status bits synchronized during transition. the solution to this potential problem is to read the bits twice for consensus.
design considerations special design considerations for conversions from dsp56166 to dsp56167 motorola dsp56167/d, rev. 1 4-15 preliminary special design considerations for conversions from dsp56166 to dsp56167 there are several areas to consider when converting a design using a dsp56166 to a design using the dsp56167. although the dsp56167 is software and pin compatible with the dsp56166, some external component changes are required. not only have additional features been added in the dsp56167, but there are also changes to existing circuitry that affect dsp operation and circuit design. in addition, several errata in the dsp56166 have been fixed in the dsp56167. the following sections provide detailed information about these design changes. note: all references to rssi are now listed as ssi. new feature descriptions new features added to the dsp56167 include: ? programmable absolute short addressing mode (pasam) ? peripheral address generation unit (pagu) ? independent external chip enable signals br and peren ? port a bg pull-down under software control ? port a and once port dr signal line keepers with reset ? external program memory access disable the following sections provide a detailed description of these new features and provide guidelines for use in applications. programmable absolute short addressing mode (pasam) previously on the dsp56166, the absolute short addressing mode allowed the user to access the first 32 locations, from x:$0000 throughx:$001f, of the data memory space using a one word move or bitfield instruction. this feature has been enhanced to allow the user to access any 32 locations within the data memory space, from x:$0000 to x:$ffff. the block of 32 locations or page of the data memory space is selected by programming the upper 11 bits of the address alu programmable absolute short addressing mode register (pasam x:$ffca), wait one instruction cycle due to the pipeline delay, and then access the new page using the same absolute short addressing mode instruction. figure 4-8 on page 4-16 shows the pasam architecture.
4-16 dsp56167/d, rev. 1 motorola design considerations special design considerations for conversions from dsp56166 to dsp56167 preliminary note: the lower 5 bits of the pasam register are reserved bits and should be written with zeros for future compatibility. they are read as zeros whenever pasam is read. the changes affect the following instructions: move(s) x:,d move(s) s,x: bftst/bfset/bfchg/bfclr#iiii,x: pasam register the register defined in figure 4-9 has been added to the dsp56100 core to allow implementation of this function. using pasam to use this function, write the starting address of the selected block into the programmable absolute short addressing mode (pasam) register to point to the desired block or page. you can access the selected block at any time. figure 4-8 programmable absolute short addressing mode architecture figure 4-9 programmable absolute short addressing mode register (pasam) gdb[15:0] pasam alu xab1[15:0] 5 11 16 ppppppppppp * * * * * 1514131211109876543210 x:$ffca where: p programmable bits; preset to 0 during processor reset * reserved bits; write 0 for future compatibility
design considerations special design considerations for conversions from dsp56166 to dsp56167 motorola dsp56167/d, rev. 1 4-17 preliminary peripheral address generation unit (pagu) a peripheral address generation unit (pagu) has been added to the dsp56167. the pagu allows the dsp to generate external peripheral addresses. to support this function, some control bits have been added to dsp56100 core registers and a number of new core registers and functional units have been added. core changes to support the pagu include: ? defined interrupt priority register (ipr2) bits 1 and 0 this is the dsp second x memory mapped interrupt priority register at address x:$ffdd. ? new registers these registers and pointers are used as matched pairs (i.e., pagur0 is used with paguc0): C peripheral address generation unit registers (pointers) 0C2 (pagur0C pagur2] C peripheral address generation unit compare registers 0C2 (paguc0C paguc2] ? new units there are two new processing units: C post update address generation unit (puagu) supports three post- update modes: ? no update [(rn)], ? post-increment [(rn)+], and ? post-decrement [(rn)C] C comparatoraddress comparator and interrupt control unit. ? new interrupt vectors there are 3 separate interrupt vectors, one for each peripheral address compare register, located at addresses p:$0030, p:$0032 and p:$0034, respectively. the interrupt feature of the pagu can be enabled by programming the two interrupt enable/priority encoding bits in the ipr2 register. the pagu interrupt can also be de-asserted if the peripheral enable (pe) bit 9 of the operating mode register (omr), (i.e., the pagu is disabled). since the hardware reset clears pe, it also deasserts the pagu interrupt request. once the pagu is enabled, every time a post update operation occurs, the post updated address will be compared against the value in the corresponding pac register. when the two values matched, an interrupt request signal will be asserted. when the dsp core recognizes the pagu interrupt, the interrupt vector corresponding to the updated peripheral address pointer is taken. its corresponding interrupt request signal is cleared as the interrupt is being serviced. if the peripheral address pointer and/or the pac register pair values are changed before the corresponding interrupt is serviced, the interrupt will remain pending.
4-18 dsp56167/d, rev. 1 motorola design considerations special design considerations for conversions from dsp56166 to dsp56167 preliminary note: the paguc0 compare interrupt has precedence over the paguc1 compare interrupt, and the paguc1 compare interrupt has precedence over the paguc2 compare interrupt. pagu programming environment the following tables and figures describe the pagu programming environment. figure 4-10 pagu with address compare interrupt architecture table 4-1 pagu x memory-mapped registers pagu register x memory mapped address pagur0 x:$ffd7 pagur1 x:$ffd6 pagur2 x:$ffd5 paguc0 x:$ffcf paguc1 x:$ffce paguc2 x:$ffcd gdb[15:0] gdb buffer pagur2 agu xab1[15:0] comparator pagur1 pagur0 paguc 2 paguc 1 paguc 0 interrupt service request
design considerations special design considerations for conversions from dsp56166 to dsp56167 motorola dsp56167/d, rev. 1 4-19 preliminary figure 4-11 interrupt priority register ipr2 (x:$ffdd) table 4-2 interrupt priority level pl1 pl0 enabled ipl 0 0 no - 0 1 yes 0 1 0 yes 1 1 1 yes 2 table 4-3 pagu interrupt vectors pagu interrupt interrupt vector address paguc0 compare interrupt p:$0030 paguc1 compare interrupt p:$0032 paguc2 compare interrupt p:$0034 table 4-4 level 3 non-maskable interrupts priority exception enabled by ip reg. bit no. control register address highest hardware reset illegal instruction stack error lowest swi 1514131211109876543210 pagu ipl irqc mode reserved ipr2 **********iclicl**plpl 21 10 note: ipr2 is reset to zero
4-20 dsp56167/d, rev. 1 motorola design considerations special design considerations for conversions from dsp56166 to dsp56167 preliminary table 4-5 level 0, 1, 2 maskable interrupts priority exception enabled by ip reg. bit no. control register address highest irqa (external interrupt) irqa mode bit 0,1 x:$ffdf irqb (external interrupt) irqb mode bit 3,4 x:$ffdf irqc (external interrupt) irqc mode bit ipr2 4,5 x:$ffdd pagu address compare 0 - ipr2 0,1 - pagu address compare 1 - ipr2 0,1 - pagu address compare 2 - ipr2 0,1 - codec rx/tx coie 6,7 x:$ffc8 host command hcie 8,9 x:$ffc4 host/dma rx data hrie 8,9 x:$ffc4 host/dma tx data htie 8,9 x:$ffc4 ssi0 rx data with exception status rie 10,11 x:$ffd1 ssi0 rx data rie 10,11 x:$ffd1 ssi0 tx data with exception status tie 10,11 x:$ffd1 ssi0 tx data tie 10,11 x:$ffd1 ssi1 rx data with exception status rie 12,13 x:$ffd9 ssi1 rx data rie 12,13 x:$ffd9 ssi1 tx data with exception status tie 12,13 x:$ffd9 ssi1 tx data tie 12,13 x:$ffd9 timer overflow oie 14,15 x:$ffec lowest timer compare oie 14,15 x:$ffec
design considerations special design considerations for conversions from dsp56166 to dsp56167 motorola dsp56167/d, rev. 1 4-21 preliminary table 4-6 interrupt vectors space mapping interrupt starting address ipl interrupt source $0000 3 hardware reset $0002 3 illegal instruction $0004 3 stack error $0006 3 reserved $0008 3 swi $000a 0-2 irqa $000c 0-2 irqb $000e 0-2 irqc $0010 0-2 ssi0 receive data with exception status $0012 0-2 ssi0 receive data $0014 0-2 ssi0transmit data with exception status $0016 0-2 ssi0 transmit data $0018 0-2 ssi1 receive data with exception status $001a 0-2 ssi1 receive data $001c 0-2 ssi1 transmit data with exception status $001e 0-2 ssi1 transmit data $0020 0-2 timer overflow $0022 0-2 timer compare $0024 0-2 host dma receive data $0026 0-2 host dma transmit data $0028 0-2 host receive data $002a 0-2 host transmit data $002c 0-2 host command (default) $002e 0-2 codec receive/transmit $0030 0-2 pagu address 0 compare $0032 0-2 pagu address 1 compare $0034 0-2 pagu address 2 compare
4-22 dsp56167/d, rev. 1 motorola design considerations special design considerations for conversions from dsp56166 to dsp56167 preliminary $0036 0-2 available for host command $0038 0-2 available for host command $003a 0-2 available for host command ... ... ... $007e 0-2 available for host command figure 4-12 dsp56100 operating mode register (omr) table 4-6 interrupt vectors space mapping (continued) interrupt starting address ipl interrupt source 1514131211109876543210 operating mode bus arbitration mode external x memory saturation rounding stop delay clockout disable peripheral agu enable reserved ******pe*cdsdrsaexmcmbma omr pe is cleared by processor reset.
design considerations special design considerations for conversions from dsp56166 to dsp56167 motorola dsp56167/d, rev. 1 4-23 preliminary figure 4-13 dsp56167 status register (sr) 1514131211109876543210 lf fv ad * s1 s0 i1 i0 s l e u n z v c ccr mr carry overflow zero negative unnormalized extension limit sticky bit interrupt mask scaling mode reserved address disable forever flag loop flag ad is cleared by processor reset
4-24 dsp56167/d, rev. 1 motorola design considerations special design considerations for conversions from dsp56166 to dsp56167 preliminary pagu operation the following figures and tables summarize pagu operation. table 4-7 pagu operation summary pe ad fast interrupt core aalu pagu 0 - - drives xab1 addr. reg. updated disabled 1 0 no drives xab1 addr. reg. updated disabled 1 - yes disabled drives xab1addr. reg. updated 1 1 - disabled drives xab1 addr. reg. updated figure 4-14 pagu operation during fast interrupt ; pe, ad reset to 0 bfset #$0200,omr nop ; pe bit set . . . move x:(r0)+,b move a,x:(r1)+ move r1,x:(r2)+ add a,bb,x:(r3)+ move x:(r0)+,x:tx move x1,y1 host fast interrupt main program pe = 1 ad = 0 (pagu not enabled) pe = 1 ad ignored (pagu enabled)
design considerations special design considerations for conversions from dsp56166 to dsp56167 motorola dsp56167/d, rev. 1 4-25 preliminary allowed move operations the pagu is used for all post update single or multi-cycle moves. the following conditions apply when using the pagu: ? bra(rn), lea(rn) and norm(rn) instructions and move instructions with - (rn), (rn+nn), and (r2+xx) addressing modes all use the core aalu registers. ? immediate and move peripheral addressing modes work as normal. ? during reduced dalu instructions with dual reads, the first parallel move is executed out of the pagu and the second parallel move is executed out of the core aalu. ? during dalu instructions with only one parallel move, the parallel move is executed from the pagu. figure 4-15 pagu operation during normal and nested long interrupt service routine ; pe, ad reset to 0 bfset #$0200,omr ; pe bit set . . . move x:(r0)+,b move a,x:(r1)+ move r1,x:(r2)+ add a,bb,x:(r3)+ . . . jsr ssi_handler . . . move x:(r0)+,x1 add x1,a . . . rti jsr tmr_handler bfclr #$2000,sr ; ad bit cleared. . . . asl a move a,x:(r1)+ . . . rti ssi interrupt handler ssi fast interrupt timer interrupt handler timer fast interrupt main program set ad set ad pe = 1 ad = 0 (pagu not enabled) pe = 1 ad = 1 (pagu enabled) pe = 1 ad = 0 (pagu not enabled)
4-26 dsp56167/d, rev. 1 motorola design considerations special design considerations for conversions from dsp56166 to dsp56167 preliminary ? during move from peripheral to x memory instruction, the x memory address comes from the pagu and the peripheral address comes from the core aalu. ? during moves to and from program memory, the program memory address is output from the core aalu and the x memory source or destination address, if needed, is output from the pagu. restrictions the following restrictions apply when using this feature: ? it is illegal to use (r3), (r3)+, (r3)-, and (rn)+nn addressing modes when the pagu is active and the r3 part of the move is not associated with a parallel move. ? modulo or reverse carry addressing modes is not allowed. ? must wait one instruction cycle before using the values written to the pagurn & pagucn registers. ? must wait one instruction cycle before using the pagu/core addressing modes after the omr[pe] and/or sr[ad} bits are changed. independent external chip enable signals br and peren on the dsp56166, while the dsp is in the master mode of bus operation, br is asserted for each external memory and external peripheral accesses. when the external peripheral space is accessed, peren is also asserted. as a result, it is possible to use br as an external chip enable. however, since both br and peren are asserted for external peripheral space accesses, it is not possible to disable or power- down an external memory versus an external peripheral separately. the dsp56167 independent chip enable feature allows the dsp to disable or power down the external memory when it is not being accessed even when the external peripheral device is being accessed. as before, the external peripheral device can be disabled using the peren pin since this signal is deasserted high whenever the external peripheral space is not being accessed. this feature is enabled when the chipen bit 15 of the bus control register2, (bcr2[15]) is set to 1. it is disabled when chipen is cleared. while in the bus master mode of operation (i.e., bit 2 of the omr is set), the user has the option of enabling br and peren to act as two independent external chip enable signals. note: this feature is not available while the chip is in the bus slave mode of operation, (i.e., omr[2] is cleared).
design considerations special design considerations for conversions from dsp56166 to dsp56167 motorola dsp56167/d, rev. 1 4-27 preliminary programming environment: a new control bit called external chip enable (echipen) has been added to the bus control register 2 (bcr2[15] at x:$ffda), to switch br and peren from their current mode of operation to the new one. external chip enable operation note: since, this feature does not alter the br and peren functions while the dsp is in the bus slave mode of operation, all subsequent discussion assume that the external bus is in the bus master mode of operation. echipen is preset to 0 during processor reset. therefore, upon coming out of reset, br and peren function as in the dsp56166. this means that br asserts during external memory access (both program and data) and during external peripheral access. peren is asserted during external peripheral accesses only. when echipen is set to 1 via software programming, br only asserts during external memory (program and data) access and peren asserts only during external peripheral accesses. if echipen is now cleared to 0 via software programming, then br and peren functionality reverts back to be the same as when the chip has just come out of reset. figure 4-16 port a bus control register 2 (bcr2), x:$ffda ec**********p4p3p2p1p0 1514131211109876543210 where: ec external chip enable; preset to 0 during processor reset p external peripheral wait states; preset to 0 during processor reset * reserved bits; write 0 for future compatibility
4-28 dsp56167/d, rev. 1 motorola design considerations special design considerations for conversions from dsp56166 to dsp56167 preliminary port a bg pull-down under software control after the bg pin is initialized high during hardware reset in bus master mode, the bg pin can be optionally pulled low by setting bus grant pull down bit (bgpd) in the bus control register (bcr[13]). this allows the dsp to become the permanent bus master while in bus master mode without having to add an external pull-up resistor. when bgpd is cleared, bg retains the last logic state that was driven by either the dsp or by an external bus master. note: bgpd is cleared by the hardware reset allowing bg to be pulled up as the default state so as not to interfere with any existing bus design. figure 4-17 external chip select operation dsp56167 memory peripheral br peren a[15:0] br peren br peren (bcr2[15]) = 0 (default) (bcr2[15]) = 1 ram access peripheral access
design considerations special design considerations for conversions from dsp56166 to dsp56167 motorola dsp56167/d, rev. 1 4-29 preliminary port a and once port dr signal line keepers with reset active pull-up and/or pull-down resistors have always been required for the external bus interface pins to keep them at a valid logic state when the dsp gives up the bus to another bus master. this is also true during hardware reset. adding on-chip static latches or keepers eliminates the need of including external resistors on board when no external memory or peripherals are attached to the dsp. when external memory and/or peripherals are desired, most if not all of the external resistors can be eliminated. the on-chip static latch for the once dr pin eliminates the need for the eternal resistor when the once is not needed. the external bus interface control signals and the once dr pins have built in reset circuitry to guarantee that they will be initialized to the desired functional state when the dsp comes out of hardware reset. figure 4-18 dsp56167 pull-up/pull-down resistors psds peren rd wr r/w bs br bg bb df a0Ca15 d0Cd15 ta dsp56166 psds peren rd wr r/w bs br bg bb df a0Ca15 d0Cd15 ta dsp56167 psds peren rd wr r/w bs br bg bb df a0Ca15 d0Cd15 ta dsp56167 10 resistors 33 resistors external pull-up/pull-down resistors required in all cases. stand-alone dsp56167 no pull-up/pull-down resistors required. 3 resistors dsp56167 with external memory/ three pull-up resistors required. (maximum). peripheral interface. * * *required only when used as outpu t enable.
4-30 dsp56167/d, rev. 1 motorola design considerations special design considerations for conversions from dsp56166 to dsp56167 preliminary external program memory access disable for those users that run strictly from internal program memory, it is now possible to disable the external program memory access as a power-saving measure. note: this has no effect on external data memory or external peripheral accesses. when this feature is enabled, the internal path from the pab bus to the port a address pins is disabled, eliminating unnecessary switching inside the dsp. external program memory access disable programming environment: a new control bit called external pab disable (epabdis) has been added to the bus control register, bcr[12] at x:$ffde, to disable the external program memory access. external program memory access disable operation epabdis is preset to 0 during processor reset. so, coming out of reset the port a bus functions exactly as the dsp56166. when epabdis is set to 1 via software programming, port a access is restricted to external data memory or external peripheral accesses. note: attempts to access external program memory while this bit is set result in an incorrect address appearing at the port a address pins. the results of the operation will be incorrect. if epabdis is cleared to 0 via software programming, then port a functionality will revert back to be the same as when the chip just came out of reset. however, due to pipeline delays inside the dsp, there should be at least 1 instruction cycle between when epabdis is cleared and external program memory is accessed. figure 4-19 port a bus control register (bcr), x:$ffde bh bs bgpdepabdis * * x4 x3 x2 x1 x0 p4 p3 p2 p1 p0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 where: bh bus request hold; preset to 0 during processor reset bs bus state status; read only bgpd bus grant pull-down; preset to 0 during processor reset epabdis external pab disable; preset to 0 during processor reset x external data memory wait states; preset to 1 during processor reset p external program memory wait states; preset to 1 during processor reset * reserved bits; write 0 for future compatibility
design considerations special design considerations for conversions from dsp56166 to dsp56167 motorola dsp56167/d, rev. 1 4-31 preliminary feature changes description changes to dsp56166 functionality in the dsp56167 include: ? codec input circuitry can be single-ended or differential ? codec input impedance is software selectable ? codec output reference voltages (vrda and vrad) are now 1/2 v dda ? codec output drive capability (for vrda, vrad, spkp, and spkm) is now 0.35 ma ? codec single-ended small signal output (spkp and spkm) impedance has changed to a range of 4.0C16.0 w for 300 hz and a range of 12.6C50.4 w for 3000 hz ? codec dac outputs (absolute single-ended) now can swing between 0.35 v and v dd C 0.4 v. refer to the section titled analog i/o considerations on page 4-4 for a detailed description of design requirements for the on-chip codec. dsp56166 chip errata fixed in the dsp56167 the following dsp56166 chip errata (some of which required hardware workarounds) have been fixed in the dsp56167: ? chkaau instruction does not operate correctly if there is a killed instruction between the last valid aalu update and chkaau ? the second read from internal data memory of a dual read instruction will transfer the wrong data if it is preceded by a conditional transfer instruction with the condition being false (i.e., the transfer is aborted). ? the once nos0 status flag does not get updated correctly when the dsp enters the wait or stop mode of operation. ? the ssi rs/tx interrupt occurs when the interrupt is enabled even though the re and te bits are cleared (i.e., function disabled). ? the ssi receiver does not operate independently from the transmitter in gated clock mode. ? in external gated clock mode, the ssi std signal can remain tri-stated during the first two bits of the transmitted word. ? in external gated clock mode, the std signal should not be tri-stated until the end of the transmitted word regardless when the te bit is cleared (i.e., the function is disabled).
4-32 dsp56167/d, rev. 1 motorola design considerations special design considerations for conversions from dsp56166 to dsp56167 preliminary ? the ssi tde and tue bits can be incorrectly set after being cleared if the clear operation is performed is performed during the last half bit period of the current word, or during the first half bit period of the next word. ? the pll may lock at the maximum vco frequency during power up at low voltage and high temperature. (the recommended workaround was to connect the sxfc to gnd and not v cc ). ? the pll lock bit failed to be asserted properly in an over-damped system. (the recommended workaround was to use a software time loop of at least 5 ms instead of the lock bit polling loop.) ? the pll may lock at the maximum vco frequency when coming out of stop mode of operation. (the workaround was to connect a 10 m w resistor between sxfc and gnd.) ? due to sxfc external filter capacitor leakage and noise, the pll frequency may jitter by as much as 25 mhz at the pll input frequency rate (output from the id divider). (the workaround was to use a faster reference clock, a smaller multiplication factor, a low-leakage capacitor for the sxfc loop filter capacitor, and to reduce the coupled noise level into the pll by careful board design.)
motorola dsp56167/d, rev. 1 5-1 preliminary section 5 ordering information dsp56167 ordering information in the table below lists the pertinent information needed to place an order. consult a motorola semiconductor sales office or authorized distributor to determine availability and to order parts. table 5-1 dsp56167 ordering information part supply voltage package type pin count frequency (mhz) order number dsp56167 5 v thin quad flat pack (tqfp) 112 60 xc56167fv60
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